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Searched refs:cpu_fpr (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfh.c.inc59 dest = cpu_fpr[a->rd];
82 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
583 tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
586 tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
601 tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
602 gen_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rd]);
H A Dtrans_rvd.c.inc66 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
90 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
551 gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
601 tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
H A Dtrans_xthead.c.inc349 TCGv_i64 rd = cpu_fpr[a->rd];
369 TCGv_i64 rd = cpu_fpr[a->rd];
454 tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
471 tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
H A Dtrans_rvzfa.c.inc412 tcg_gen_sari_i64(t1, cpu_fpr[a->rs1], 32);
427 tcg_gen_concat_tl_i64(cpu_fpr[a->rd], src1, src2);
H A Dtrans_rvf.c.inc57 dest = cpu_fpr[a->rd];
79 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
H A Dtrans_rvv.c.inc2285 do_nanbox(s, t1, cpu_fpr[rs1]);
2630 do_nanbox(s, t1, cpu_fpr[a->rs1]);
2648 do_nanbox(s, t1, cpu_fpr[a->rs1]);
3340 vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
3344 tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
3373 do_nanbox(s, t1, cpu_fpr[a->rs1]);
/openbmc/qemu/target/loongarch/
H A Dtranslate.h58 extern TCGv_i64 cpu_fpr[32];
/openbmc/qemu/target/riscv/
H A Dtranslate.c41 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ variable
443 return cpu_fpr[reg_num]; in get_fpr_hs()
470 return cpu_fpr[reg_num]; in get_fpr_d()
495 return cpu_fpr[reg_num]; in dest_fpr()
518 tcg_gen_mov_i64(cpu_fpr[reg_num], t); in gen_set_fpr_hs()
542 tcg_gen_mov_i64(cpu_fpr[reg_num], t); in gen_set_fpr_d()
1376 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, in riscv_translate_init()