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Searched refs:cmdq_base (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_tlv.h48 static inline u8 __get_cmdq_base_opcode(struct cmdq_base *req, u32 size) in __get_cmdq_base_opcode()
51 return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode; in __get_cmdq_base_opcode()
56 static inline void __set_cmdq_base_opcode(struct cmdq_base *req, in __set_cmdq_base_opcode()
60 ((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val; in __set_cmdq_base_opcode()
65 static inline __le16 __get_cmdq_base_cookie(struct cmdq_base *req, u32 size) in __get_cmdq_base_cookie()
68 return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie; in __get_cmdq_base_cookie()
73 static inline void __set_cmdq_base_cookie(struct cmdq_base *req, in __set_cmdq_base_cookie()
77 ((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val; in __set_cmdq_base_cookie()
82 static inline __le64 __get_cmdq_base_resp_addr(struct cmdq_base *req, u32 size) in __get_cmdq_base_resp_addr()
85 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr; in __get_cmdq_base_resp_addr()
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H A Dqplib_rcfw.h63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req, in bnxt_qplib_rcfw_cmd_prep()
97 static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req) in bnxt_qplib_get_cmd_slots()
113 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req) in bnxt_qplib_set_cmd_slots()
240 struct cmdq_base *req;
H A Dqplib_sp.c77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_version()
105 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_get_dev_attr()
209 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_set_func_resources()
278 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_del_sgid()
347 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_add_sgid()
410 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_update_sgid()
449 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_ah()
494 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_ah()
520 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_free_mrw()
555 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_alloc_mrw()
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H A Dqplib_rcfw.c457 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in __destroy_timedout_ah()
461 msg.req = (struct cmdq_base *)&req; in __destroy_timedout_ah()
815 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_deinit_rcfw()
837 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_init_rcfw()
H A Dqplib_fp.c607 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_srq()
643 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_srq()
729 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_srq()
840 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp1()
986 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp()
1285 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_modify_qp()
1399 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_qp()
1532 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_qp()
2164 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_cq()
2229 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_resize_cq()
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H A Droce_hsi.h104 struct cmdq_base { struct
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ethdr.c71 struct cmdq_client_reg cmdq_base; member
169 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); in mtk_ethdr_layer_config()
189 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, in mtk_ethdr_layer_config()
191 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); in mtk_ethdr_layer_config()
192 mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), in mtk_ethdr_layer_config()
194 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, in mtk_ethdr_layer_config()
212 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
215 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
218 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
221 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
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/openbmc/linux/drivers/soc/mediatek/
H A Dmtk-mmsys.c137 struct cmdq_client_reg cmdq_base; member
146 if (mmsys->cmdq_base.size && cmdq_pkt) { in mtk_mmsys_update_bits()
147 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, in mtk_mmsys_update_bits()
148 mmsys->cmdq_base.offset + offset, val, in mtk_mmsys_update_bits()
386 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); in mtk_mmsys_probe()
/openbmc/linux/drivers/accel/ivpu/
H A Dvpu_jsm_api.h622 u64 cmdq_base; member
692 u64 cmdq_base; member