Home
last modified time | relevance | path

Searched refs:clrsetbits_le32 (Results 1 – 25 of 240) sorted by relevance

12345678910

/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c135 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_34xx()
146 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
148 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
152 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
156 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
160 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
167 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
170 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
173 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
176 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
[all …]
H A Dam35x_musb.c18 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, in am35x_musb_reset()
20 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, in am35x_musb_reset()
32 clrsetbits_le32(&am35x_scm_general_regs->devconf2, in am35x_musb_phy_power()
49 clrsetbits_le32(&am35x_scm_general_regs->devconf2, in am35x_musb_phy_power()
57 clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, in am35x_musb_clear_irq()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c134 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); in set_memory_map()
135 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), in set_memory_map()
139 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), in set_memory_map()
143 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); in set_memory_map()
146 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), in set_memory_map()
150 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); in set_memory_map()
214 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); in set_ds_odt()
215 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); in set_ds_odt()
216 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); in set_ds_odt()
217 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); in set_ds_odt()
[all …]
/openbmc/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c273 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
275 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
282 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
287 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
293 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
296 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, in clock_init()
[all …]
/openbmc/u-boot/board/toradex/colibri_vf/
H A Dcolibri_vf.c382 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
387 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
389 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
393 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
395 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
398 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
400 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
402 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
404 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
411 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | in clock_init()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-tegra.c318 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, in init_phy_mux()
322 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, in init_phy_mux()
328 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, in init_phy_mux()
337 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, in init_phy_mux()
367 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, in init_utmi_usb_controller()
376 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, in init_utmi_usb_controller()
391 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, in init_utmi_usb_controller()
394 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, in init_utmi_usb_controller()
401 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, in init_utmi_usb_controller()
404 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, in init_utmi_usb_controller()
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c120 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); in board_clock_init()
130 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); in board_clock_init()
139 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); in board_clock_init()
163 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
178 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
204 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); in board_clock_init()
213 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); in board_clock_init()
224 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); in board_clock_init()
248 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
271 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
[all …]
/openbmc/u-boot/board/phytec/pcm052/
H A Dpcm052.c467 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
469 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
471 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
476 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
478 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
481 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
483 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
485 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
487 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
490 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, in clock_init()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c129 clrsetbits_le32(&power_regs->hw_power_vdddctrl, in mxs_power_set_linreg()
134 clrsetbits_le32(&power_regs->hw_power_vddactrl, in mxs_power_set_linreg()
139 clrsetbits_le32(&power_regs->hw_power_vddioctrl, in mxs_power_set_linreg()
191 clrsetbits_le32(&power_regs->hw_power_5vctrl, in mxs_is_batt_good()
197 clrsetbits_le32(&power_regs->hw_power_charge, in mxs_is_batt_good()
243 clrsetbits_le32(&power_regs->hw_power_5vctrl, in mxs_power_setup_5v_detect()
262 clrsetbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
299 clrsetbits_le32(&power_regs->hw_power_dclimits, in mxs_src_power_init()
307 clrsetbits_le32(&power_regs->hw_power_loopctrl, in mxs_src_power_init()
312 clrsetbits_le32(&power_regs->hw_power_minpwr, in mxs_src_power_init()
[all …]
H A Dspl_lradc_init.c26 clrsetbits_le32(&regs->hw_lradc_ctrl3, in mxs_lradc_init()
30 clrsetbits_le32(&regs->hw_lradc_ctrl4, in mxs_lradc_init()
54 clrsetbits_le32(&regs->hw_lradc_conversion, in mxs_lradc_enable_batt_measurement()
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c157 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
161 clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
165 clrsetbits_le32(&cmwkup->wkup_uart0ctrl, in setup_clocks_for_console()
169 clrsetbits_le32(&cmper->uart1clkctrl, in setup_clocks_for_console()
173 clrsetbits_le32(&cmper->uart2clkctrl, in setup_clocks_for_console()
177 clrsetbits_le32(&cmper->uart3clkctrl, in setup_clocks_for_console()
181 clrsetbits_le32(&cmper->uart4clkctrl, in setup_clocks_for_console()
185 clrsetbits_le32(&cmper->uart5clkctrl, in setup_clocks_for_console()
H A Dclock.c35 clrsetbits_le32(dpll_regs->cm_clkmode_dpll, in do_lock_dpll()
52 clrsetbits_le32(dpll_regs->cm_clkmode_dpll, in do_bypass_dpll()
139 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in enable_clock_module()
165 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, in disable_clock_module()
175 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in enable_clock_domain()
182 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, in disable_clock_domain()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c217 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
219 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
278 clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); in mctl_channel_init()
282 clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
294 clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
296 clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
298 clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
300 clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16), in mctl_channel_init()
305 clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26); in mctl_channel_init()
324 clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) , in mctl_channel_init()
[all …]
H A Ddram_sun50i_h6.c260 clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); in mctl_set_timing_lpddr3()
262 clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); in mctl_set_timing_lpddr3()
445 clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); in mctl_com_init()
541 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0); in mctl_channel_init()
543 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800)); in mctl_channel_init()
545 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220); in mctl_channel_init()
547 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); in mctl_channel_init()
551 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); in mctl_channel_init()
553 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); in mctl_channel_init()
555 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); in mctl_channel_init()
[all …]
H A Ddram_sunxi_dw.c283 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, in mctl_h3_zq_calibration_quirk()
385 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
393 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
437 clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); in mctl_channel_init()
442 clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
457 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
461 clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, in mctl_channel_init()
472 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
476 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
483 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
[all …]
H A Ddram_sun4i.c103 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
105 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
115 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
137 clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, in mctl_enable_dll0()
139 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); in mctl_enable_dll0()
145 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); in mctl_enable_dll0()
171 clrsetbits_le32(&dram->dllcr[i], 0xf << 14, in mctl_enable_dllx()
173 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, in mctl_enable_dllx()
185 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, in mctl_enable_dllx()
655 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); in dramc_init_helper()
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c266 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); in cpt_pm_init()
283 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in cpt_pm_init()
287 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in cpt_pm_init()
291 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); in cpt_pm_init()
292 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in cpt_pm_init()
309 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); in ppt_pm_init()
325 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in ppt_pm_init()
329 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in ppt_pm_init()
335 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); in ppt_pm_init()
336 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in ppt_pm_init()
[all …]
/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c232 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); in stm32_ltdc_set_mode()
236 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); in stm32_ltdc_set_mode()
240 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); in stm32_ltdc_set_mode()
244 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); in stm32_ltdc_set_mode()
259 clrsetbits_le32(regs + LTDC_GCR, in stm32_ltdc_set_mode()
284 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, in stm32_ltdc_set_layer1()
290 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, in stm32_ltdc_set_layer1()
302 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); in stm32_ltdc_set_layer1()
306 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format); in stm32_ltdc_set_layer1()
309 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); in stm32_ltdc_set_layer1()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Ddra7xx_iodelay.c21 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
23 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
28 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
35 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
41 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
62 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, in calibrate_iodelay()
74 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, in update_delay_mechanism()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610-calibration.c113 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
117 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
121 do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
187 clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3), in ddrmc_cal_dqs_to_dq()
209 clrsetbits_le32(&ddrmr->cr[105], in ddrmc_cal_dqs_to_dq()
261 clrsetbits_le32(&ddrmr->cr[110], in ddrmc_cal_dqs_to_dq()
/openbmc/u-boot/board/sunxi/
H A Dahci.c26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
/openbmc/u-boot/drivers/gpio/
H A Drk_gpio.c49 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0); in rockchip_gpio_direction_output()
70 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0); in rockchip_gpio_set_value()
122 clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2)); in spl_gpio_set_pull()
131 clrsetbits_le32(&regs->swport_dr, 1 << gpio, value << gpio); in spl_gpio_output()
134 clrsetbits_le32(&regs->swport_ddr, 1 << gpio, 1 << gpio); in spl_gpio_output()
/openbmc/u-boot/drivers/mmc/
H A Dmtk-sd.c688 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, in msdc_set_timeout()
781 clrsetbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
788 clrsetbits_le32(&host->base->msdc_cfg, in msdc_set_mclk()
954 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, in msdc_tune_response()
961 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, in msdc_tune_response()
983 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, in msdc_tune_response()
1003 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, in msdc_tune_response()
1009 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, in msdc_tune_response()
1019 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, in msdc_tune_response()
1030 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, in msdc_tune_response()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c864 clrsetbits_le32(addr, clear_bit, set_bit); in exynos4_set_mmc_clk()
887 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), in exynos5_set_mmc_clk()
908 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); in exynos5420_set_mmc_clk()
1088 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); in exynos4_set_lcd_clk()
1112 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1140 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); in exynos5_set_lcd_clk()
1164 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
1213 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); in exynos5800_set_lcd_clk()
1229 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); in exynos4_set_mipi_clk()
1263 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3399_vop.c31 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
37 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
43 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()

12345678910