| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | eth_hydra.c | 107 clrsetbits_8(&pixis->brdcfg1, mask, val); in hydra_mux_mdio()
499 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, in board_eth_init()
505 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, in board_eth_init()
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| H A D | eth_superhydra.c | 112 clrsetbits_8(&pixis->brdcfg1, mask, val); in super_hydra_mux_mdio()
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| /openbmc/u-boot/board/freescale/common/ |
| H A D | pixis.c | 112 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); in set_px_mpxpll()
148 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); in set_px_corepll()
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| /openbmc/u-boot/board/freescale/p1022ds/ |
| H A D | spl.c | 46 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); in board_init_f()
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| H A D | p1022ds.c | 48 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); in board_early_init_f()
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| /openbmc/u-boot/arch/sandbox/include/asm/ |
| H A D | io.h | 110 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
166 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/lib/ |
| H A D | uuid.c | 249 clrsetbits_8(&uuid.clock_seq_hi_and_reserved, in gen_rand_uuid()
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| /openbmc/u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | cpu_init.c | 423 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK, in fecpin_setclear()
425 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK, in fecpin_setclear()
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| /openbmc/u-boot/arch/x86/cpu/ivybridge/ |
| H A D | northbridge.c | 119 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); in northbridge_init()
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| H A D | lpc.c | 422 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); in set_spi_speed()
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| /openbmc/linux/arch/powerpc/platforms/85xx/ |
| H A D | mpc85xx_mds.c | 214 clrsetbits_8(&bcsr_regs[7 + ucc_num], in mpc85xx_mds_reset_ucc_phys()
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| /openbmc/u-boot/arch/nios2/include/asm/ |
| H A D | io.h | 166 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/arc/include/asm/ |
| H A D | io.h | 278 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/drivers/spi/ |
| H A D | sh_qspi.c | 191 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG, in sh_qspi_xfer_common()
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| H A D | bcm63xx_spi.c | 171 clrsetbits_8(priv->base + regs[SPI_CLK], in bcm63xx_spi_set_speed()
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | io.h | 245 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | fsl_gtm.c | 209 clrsetbits_8(tmr->gtcfr, ~(GTCFR_STP(num) | GTCFR_RST(num)), in gtm_set_ref_timer16()
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | io.h | 232 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | io.h | 129 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/x86/cpu/broadwell/ |
| H A D | pch.c | 446 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ in systemagent_init()
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | io.h | 283 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/nds32/include/asm/ |
| H A D | io.h | 210 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/riscv/include/asm/ |
| H A D | io.h | 197 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | io.h | 206 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | io.h | 1048 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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