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Searched refs:clk_mux_uart0_p (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi3660.c250 clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",}; variable
272 { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
273 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
H A Dclk-hi3670.c381 clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", }; variable
448 { HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
449 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,