| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 21 u32 clk_id; member
52 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode() local
57 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); in zynqmp_pll_get_mode()
75 u32 clk_id = clk->clk_id; in zynqmp_pll_set_mode() local
85 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); in zynqmp_pll_set_mode()
137 u32 clk_id = clk->clk_id; in zynqmp_pll_recalc_rate() local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
158 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); in zynqmp_pll_recalc_rate()
181 u32 clk_id = clk->clk_id; in zynqmp_pll_set_rate() local
197 ret = zynqmp_pm_clock_setdivider(clk_id, m); in zynqmp_pll_set_rate()
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| H A D | clk-gate-zynqmp.c | 23 u32 clk_id; member
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable() local
41 ret = zynqmp_pm_clock_enable(clk_id); in zynqmp_clk_gate_enable()
45 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_enable()
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable() local
61 ret = zynqmp_pm_clock_disable(clk_id); in zynqmp_clk_gate_disable()
65 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_disable()
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled() local
81 ret = zynqmp_pm_clock_getstate(clk_id, &state); in zynqmp_clk_gate_is_enabled()
107 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, in zynqmp_clk_register_gate() argument
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| H A D | clkc.c | 79 u32 clk_id; member
122 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
146 static inline int zynqmp_is_valid_clock(u32 clk_id) in zynqmp_is_valid_clock() argument
148 if (clk_id >= clock_max_idx) in zynqmp_is_valid_clock()
151 return clock[clk_id].valid; in zynqmp_is_valid_clock()
161 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
165 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_name()
167 strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
181 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) in zynqmp_get_clock_type() argument
185 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_type()
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| H A D | divider.c | 44 u32 clk_id; member
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate() local
89 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
127 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate() local
135 ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); in zynqmp_clk_divider_round_rate()
174 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate() local
191 ret = zynqmp_pm_clock_setdivider(clk_id, div); in zynqmp_clk_divider_set_rate()
219 static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) in zynqmp_clk_get_max_divisor() argument
226 qdata.arg1 = clk_id; in zynqmp_clk_get_max_divisor()
273 u32 clk_id, in zynqmp_clk_register_divider() argument
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| H A D | clk-mux-zynqmp.c | 32 u32 clk_id; member
47 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_get_parent() local
51 ret = zynqmp_pm_clock_getparent(clk_id, &val); in zynqmp_clk_mux_get_parent()
77 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_set_parent() local
80 ret = zynqmp_pm_clock_setparent(clk_id, index); in zynqmp_clk_mux_set_parent()
131 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, in zynqmp_clk_register_mux() argument
157 mux->clk_id = clk_id; in zynqmp_clk_register_mux()
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| H A D | clk-zynqmp.h | 70 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
75 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
81 u32 clk_id,
86 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
92 u32 clk_id,
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| /openbmc/linux/drivers/clk/keystone/ |
| H A D | sci-clk.c | 54 u32 clk_id; member
79 clk->clk_id, enable_ssc, in sci_clk_prepare()
96 clk->clk_id); in sci_clk_unprepare()
100 clk->dev_id, clk->clk_id, ret); in sci_clk_unprepare()
117 clk->clk_id, &req_state, in sci_clk_is_prepared()
122 clk->dev_id, clk->clk_id, ret); in sci_clk_is_prepared()
145 clk->clk_id, &freq); in sci_clk_recalc_rate()
149 clk->dev_id, clk->clk_id, ret); in sci_clk_recalc_rate()
180 clk->clk_id, in sci_clk_determine_rate()
188 clk->dev_id, clk->clk_id, ret); in sci_clk_determine_rate()
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| /openbmc/linux/tools/testing/selftests/timens/ |
| H A D | timens.h | 64 static inline int _settime(clockid_t clk_id, time_t offset) in _settime() argument
69 if (clk_id == CLOCK_MONOTONIC_COARSE || clk_id == CLOCK_MONOTONIC_RAW) in _settime()
70 clk_id = CLOCK_MONOTONIC; in _settime()
72 len = snprintf(buf, sizeof(buf), "%d %ld 0", clk_id, offset); in _settime()
86 static inline int _gettime(clockid_t clk_id, struct timespec *res, bool raw_syscall) in _gettime() argument
91 if (clock_gettime(clk_id, res)) { in _gettime()
92 pr_perror("clock_gettime(%d)", (int)clk_id); in _gettime()
98 err = syscall(SYS_clock_gettime, clk_id, res); in _gettime()
100 pr_perror("syscall(SYS_clock_gettime(%d))", (int)clk_id); in _gettime()
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| /openbmc/linux/drivers/pmdomain/mediatek/ |
| H A D | mtk-scpsys.c | 81 enum clk_id { enum
129 enum clk_id clk_id[MAX_CLKS]; member
496 for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { in init_scp()
497 struct clk *c = clk[data->clk_id[j]]; in init_scp()
564 .clk_id = {CLK_NONE},
572 .clk_id = {CLK_MM},
582 .clk_id = {CLK_MFG},
591 .clk_id = {CLK_MM},
600 .clk_id = {CLK_MM},
608 .clk_id = {CLK_NONE},
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| /openbmc/linux/drivers/firmware/arm_scmi/ |
| H A D | clock.c | 86 __le32 clk_id; member
136 u32 clk_id, struct scmi_clock_info *clk, in scmi_clock_attributes_get() argument
145 sizeof(clk_id), sizeof(*attr), &t); in scmi_clock_attributes_get()
149 put_unaligned_le32(clk_id, t->tx.buf); in scmi_clock_attributes_get()
171 ph->hops->extended_name_get(ph, CLOCK_NAME_GET, clk_id, in scmi_clock_attributes_get()
198 u32 clk_id; member
209 msg->id = cpu_to_le32(p->clk_id); in iter_clk_describe_prepare_message()
288 scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id, in scmi_clock_describe_rates_get() argument
299 .clk_id = clk_id, in scmi_clock_describe_rates_get()
329 u32 clk_id, u64 *value) in scmi_clock_rate_get() argument
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| /openbmc/linux/tools/testing/selftests/vDSO/ |
| H A D | vdso_test_abi.c | 32 typedef long (*vdso_clock_gettime_t)(clockid_t clk_id, struct timespec *ts);
33 typedef long (*vdso_clock_getres_t)(clockid_t clk_id, struct timespec *ts);
63 static void vdso_test_clock_gettime(clockid_t clk_id) in vdso_test_clock_gettime() argument
75 long ret = vdso_clock_gettime(clk_id, &ts); in vdso_test_clock_gettime()
108 static void vdso_test_clock_getres(clockid_t clk_id) in vdso_test_clock_getres() argument
122 long ret = vdso_clock_getres(clk_id, &ts); in vdso_test_clock_getres()
131 ret = syscall(SYS_clock_getres, clk_id, &sys_ts); in vdso_test_clock_getres()
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| /openbmc/u-boot/drivers/firmware/ |
| H A D | ti_sci.c | 790 u32 dev_id, u8 clk_id, in ti_sci_set_clock_state() argument
815 req.clk_id = clk_id; in ti_sci_set_clock_state()
845 u32 dev_id, u8 clk_id, in ti_sci_cmd_get_clock_state() argument
873 req.clk_id = clk_id; in ti_sci_cmd_get_clock_state()
908 u8 clk_id, bool needs_ssc, bool can_change_freq, in ti_sci_cmd_get_clock() argument
917 return ti_sci_set_clock_state(handle, dev_id, clk_id, flags, in ti_sci_cmd_get_clock()
934 u32 dev_id, u8 clk_id) in ti_sci_cmd_idle_clock() argument
936 return ti_sci_set_clock_state(handle, dev_id, clk_id, 0, in ti_sci_cmd_idle_clock()
953 u32 dev_id, u8 clk_id) in ti_sci_cmd_put_clock() argument
955 return ti_sci_set_clock_state(handle, dev_id, clk_id, 0, in ti_sci_cmd_put_clock()
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| H A D | ti_sci.h | 269 u8 clk_id; member
290 u8 clk_id; member
328 u8 clk_id; member
345 u8 clk_id; member
376 u8 clk_id; member
419 u8 clk_id; member
475 u8 clk_id; member
493 u8 clk_id; member
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| /openbmc/linux/sound/soc/ti/ |
| H A D | omap-dmic.c | 279 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_fclk() argument
298 if (dmic->sysclk == clk_id) { in omap_dmic_select_fclk()
309 switch (clk_id) { in omap_dmic_select_fclk()
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
353 dmic->sysclk = clk_id; in omap_dmic_select_fclk()
363 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_outclk() argument
368 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) { in omap_dmic_select_outclk()
370 clk_id); in omap_dmic_select_outclk()
390 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, in omap_dmic_set_dai_sysclk() argument
396 return omap_dmic_select_fclk(dmic, clk_id, freq); in omap_dmic_set_dai_sysclk()
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| /openbmc/linux/drivers/firmware/ |
| H A D | ti_sci.c | 943 u32 dev_id, u32 clk_id, in ti_sci_set_clock_state() argument
971 if (clk_id < 255) { in ti_sci_set_clock_state()
972 req->clk_id = clk_id; in ti_sci_set_clock_state()
974 req->clk_id = 255; in ti_sci_set_clock_state()
975 req->clk_id_32 = clk_id; in ti_sci_set_clock_state()
1008 u32 dev_id, u32 clk_id, in ti_sci_cmd_get_clock_state() argument
1039 if (clk_id < 255) { in ti_sci_cmd_get_clock_state()
1040 req->clk_id = clk_id; in ti_sci_cmd_get_clock_state()
1042 req->clk_id = 255; in ti_sci_cmd_get_clock_state()
1043 req->clk_id_32 = clk_id; in ti_sci_cmd_get_clock_state()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 38 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
41 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll()
239 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
243 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate()
257 shift = clk_shift[clk_id]; in rkclk_pll_get_rate()
258 mask = clk_mask[clk_id]; in rkclk_pll_get_rate()
346 static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id) in rk3128_peri_get_pclk() argument
350 switch (clk_id) { in rk3128_peri_get_pclk()
367 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk() argument
374 switch (clk_id) { in rk3128_peri_set_pclk()
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| H A D | clk_rk3399.c | 515 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) in rk3399_i2c_get_clk() argument
519 switch (clk_id) { in rk3399_i2c_get_clk()
552 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_i2c_set_clk() argument
560 switch (clk_id) { in rk3399_i2c_set_clk()
590 return rk3399_i2c_get_clk(cru, clk_id); in rk3399_i2c_set_clk()
629 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) in rk3399_spi_get_clk() argument
634 switch (clk_id) { in rk3399_spi_get_clk()
636 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3399_spi_get_clk()
640 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3399_spi_get_clk()
651 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_spi_set_clk() argument
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| H A D | clk_rk3368.c | 157 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) in rk3368_mmc_get_clk() argument
162 switch (clk_id) { in rk3368_mmc_get_clk()
253 ulong clk_id = clk->id; in rk3368_mmc_set_clk() local
259 switch (clk_id) { in rk3368_mmc_set_clk()
277 return rk3368_mmc_get_clk(cru, clk_id); in rk3368_mmc_set_clk()
378 static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id) in rk3368_spi_get_clk() argument
383 switch (clk_id) { in rk3368_spi_get_clk()
385 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_get_clk()
389 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3368_spi_get_clk()
400 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk() argument
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra-audio.c | 35 int clk_id; member
41 .clk_id = tegra_clk_ ## _name,\
66 int clk_id; member
77 .clk_id = tegra_clk_ ## _name ## _2x,\
181 dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks); in tegra_audio_clk_init()
207 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
231 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
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| H A D | clk.c | 262 for (; dup_list->clk_id < clk_max; dup_list++) { in tegra_init_dup_clks()
263 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
274 for (; tbl->clk_id < clk_max; tbl++) { in tegra_init_from_table()
275 clk = clks[tbl->clk_id]; in tegra_init_from_table()
278 __func__, PTR_ERR(clk), tbl->clk_id); in tegra_init_from_table()
373 struct clk ** __init tegra_lookup_dt_id(int clk_id, in tegra_lookup_dt_id() argument
376 if (tegra_clk[clk_id].present) in tegra_lookup_dt_id()
377 return &clks[tegra_clk[clk_id].dt_id]; in tegra_lookup_dt_id()
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | adav80x.c | 538 int clk_id, int source, in adav80x_set_sysclk() argument
545 switch (clk_id) { in adav80x_set_sysclk()
558 if (adav80x->clk_src != clk_id) { in adav80x_set_sysclk()
561 adav80x->clk_src = clk_id; in adav80x_set_sysclk()
562 if (clk_id == ADAV80X_CLK_XTAL) in adav80x_set_sysclk()
563 clk_id = ADAV80X_CLK_XIN; in adav80x_set_sysclk()
565 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | in adav80x_set_sysclk()
566 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | in adav80x_set_sysclk()
567 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); in adav80x_set_sysclk()
568 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); in adav80x_set_sysclk()
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| /openbmc/linux/tools/perf/util/ |
| H A D | clockid.c | 55 static int get_clockid_res(clockid_t clk_id, u64 *res_ns) in get_clockid_res() argument
60 if (!clock_getres(clk_id, &res)) in get_clockid_res()
110 const char *clockid_name(clockid_t clk_id) in clockid_name() argument
115 if (cm->clockid == clk_id) in clockid_name()
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| /openbmc/linux/sound/soc/qcom/qdsp6/ |
| H A D | q6prm.c | 112 static int q6prm_request_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_request_lpass_clock() argument
137 req->clock_id.clock_id = clk_id; in q6prm_request_lpass_clock()
149 static int q6prm_release_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_release_lpass_clock() argument
174 rel->clock_id.clock_id = clk_id; in q6prm_release_lpass_clock()
183 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, in q6prm_set_lpass_clock() argument
187 return q6prm_request_lpass_clock(dev, clk_id, clk_attr, clk_root, freq); in q6prm_set_lpass_clock()
189 return q6prm_release_lpass_clock(dev, clk_id, clk_attr, clk_root, freq); in q6prm_set_lpass_clock()
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| H A D | q6dsp-lpass-clocks.h | 7 int clk_id; member
14 .clk_id = id, \
22 int (*lpass_set_clk)(struct device *dev, int clk_id, int attr,
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | clk-ccu-pll.c | 87 unsigned int clk_id) in ccu_pll_find_desc() argument
92 if (pll_info[idx].id == clk_id) in ccu_pll_find_desc()
134 unsigned int clk_id; in ccu_pll_of_clk_hw_get() local
136 clk_id = clkspec->args[0]; in ccu_pll_of_clk_hw_get()
137 pll = ccu_pll_find_desc(data, clk_id); in ccu_pll_of_clk_hw_get()
140 pr_info("Invalid PLL clock ID %d specified\n", clk_id); in ccu_pll_of_clk_hw_get()
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