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Searched refs:cfg (Results 1 – 25 of 2502) sorted by relevance

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/openbmc/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
44 cfg->clk_term_en = 0; in phy_mipi_dphy_calc_config()
45 cfg->clk_trail = 60000; in phy_mipi_dphy_calc_config()
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
[all …]
/openbmc/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
[all …]
/openbmc/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
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/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h53 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
54 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
55 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
56 #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind) argument
57 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
58 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
59 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
61 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
62 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
63 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
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/openbmc/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy_tbl.h45 PHY_ENGINE cfg; member
54 .cfg.fp_set = phy_realtek5,
55 .cfg.fp_clr = recov_phy_realtek5 },
60 .cfg.fp_set = phy_realtek5,
61 .cfg.fp_clr = recov_phy_realtek5 },
66 .cfg.fp_set = phy_realtek5,
67 .cfg.fp_clr = recov_phy_realtek5 },
72 .cfg.fp_set = phy_realtek2,
73 .cfg.fp_clr = recov_phy_realtek2 },
78 .cfg.fp_set = phy_realtek1,
[all …]
/openbmc/linux/drivers/pci/
H A Decam.c32 struct pci_config_window *cfg; in pci_ecam_create() local
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
41 if (!cfg) in pci_ecam_create()
48 cfg->parent = dev; in pci_ecam_create()
49 cfg->ops = ops; in pci_ecam_create()
50 cfg->busr.start = busr->start; in pci_ecam_create()
51 cfg->busr.end = busr->end; in pci_ecam_create()
52 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
53 cfg->bus_shift = bus_shift; in pci_ecam_create()
54 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
[all …]
/openbmc/u-boot/drivers/video/
H A Dssd2828.c153 static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) in read_hw_register() argument
155 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in read_hw_register()
156 return soft_spi_xfer_24bit_3wire(cfg, 0x730000); in read_hw_register()
162 static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, in write_hw_register() argument
165 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in write_hw_register()
166 soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); in write_hw_register()
172 static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) in send_mipi_dcs_command() argument
175 write_hw_register(cfg, SSD2828_PSCR1, 1); in send_mipi_dcs_command()
177 write_hw_register(cfg, SSD2828_PDR, cmdnum); in send_mipi_dcs_command()
183 static void ssd2828_reset(const struct ssd2828_config *cfg) in ssd2828_reset() argument
[all …]
/openbmc/linux/sound/pci/hda/
H A Dhda_auto_parser.c56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
173 struct auto_pin_cfg *cfg, in snd_hda_parse_pin_defcfg() argument
179 struct auto_out_pin line_out[ARRAY_SIZE(cfg->line_out_pins)]; in snd_hda_parse_pin_defcfg()
180 struct auto_out_pin speaker_out[ARRAY_SIZE(cfg->speaker_pins)]; in snd_hda_parse_pin_defcfg()
181 struct auto_out_pin hp_out[ARRAY_SIZE(cfg->hp_pins)]; in snd_hda_parse_pin_defcfg()
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c133 u64 cfg, last; in rpm_lmac_tx_enable() local
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
153 u64 cfg; in rpm_lmac_rx_tx_enable() local
158 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
160 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
[all …]
/openbmc/linux/arch/x86/pci/
H A Dmmconfig-shared.c37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
39 if (cfg->res.parent) in pci_mmconfig_remove()
40 release_resource(&cfg->res); in pci_mmconfig_remove()
41 list_del(&cfg->list); in pci_mmconfig_remove()
42 kfree(cfg); in pci_mmconfig_remove()
47 struct pci_mmcfg_region *cfg, *tmp; in free_all_mmcfg() local
50 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) in free_all_mmcfg()
51 pci_mmconfig_remove(cfg); in free_all_mmcfg()
56 struct pci_mmcfg_region *cfg; in list_add_sorted() local
59 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { in list_add_sorted()
[all …]
H A Dmmconfig_64.c21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
99 static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg) in mcfg_ioremap() argument
105 start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
106 num_buses = cfg->end_bus - cfg->start_bus + 1; in mcfg_ioremap()
110 addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
116 struct pci_mmcfg_region *cfg; in pci_mmcfg_arch_init() local
118 list_for_each_entry(cfg, &pci_mmcfg_list, list) in pci_mmcfg_arch_init()
119 if (pci_mmcfg_arch_map(cfg)) { in pci_mmcfg_arch_init()
[all …]
/openbmc/qemu/tests/qtest/
H A Dsifive-e-aon-watchdog-test.c182 uint32_t cfg; in test_scaled_wdogs() local
195 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_scaled_wdogs()
196 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, i); in test_scaled_wdogs()
198 qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); in test_scaled_wdogs()
201 FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE))); in test_scaled_wdogs()
209 uint32_t cfg; in test_watchdog() local
217 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_watchdog()
218 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0); in test_watchdog()
219 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); in test_watchdog()
221 qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); in test_watchdog()
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_gsc.c65 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
380 u32 cfg; in gsc_sw_reset() local
384 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
385 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
389 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
390 if (!cfg) in gsc_sw_reset()
395 if (cfg) { in gsc_sw_reset()
401 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
402 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
404 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
[all …]
H A Dexynos_drm_fimc.c139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8996.c219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
/openbmc/qemu/target/microblaze/
H A Dcpu.c128 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { in mb_cpu_mmu_index()
142 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; in mb_cpu_ns_axi_dp()
150 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; in mb_cpu_ns_axi_ip()
158 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; in mb_cpu_ns_axi_dc()
166 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; in mb_cpu_ns_axi_ic()
202 env->pc = cpu->cfg.base_vectors; in mb_cpu_reset_hold()
242 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { in mb_cpu_realizefn()
244 cpu->cfg.addr_size); in mb_cpu_realizefn()
250 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; in mb_cpu_realizefn()
259 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); in mb_cpu_realizefn()
[all …]
/openbmc/linux/drivers/scsi/cxlflash/
H A Dmain.c45 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err() local
46 struct device *dev = &cfg->dev->dev; in process_cmd_err()
157 struct cxlflash_cfg *cfg = afu->parent; in cmd_complete() local
158 struct device *dev = &cfg->dev->dev; in cmd_complete()
176 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in cmd_complete()
177 cfg->tmf_active = false; in cmd_complete()
178 wake_up_all_locked(&cfg->tmf_waitq); in cmd_complete()
179 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); in cmd_complete()
193 struct cxlflash_cfg *cfg = hwq->afu->parent; in flush_pending_cmds() local
213 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in flush_pending_cmds()
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/openbmc/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcore_extern.c25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
65 { .name = "bool (n)", .cfg = CFG"CONFIG_BOOL=n\n",
67 { .name = "bool (tristate)", .fails = 1, .cfg = CFG"CONFIG_BOOL=m" },
[all …]
/openbmc/qemu/util/
H A Dthrottle.c73 throttle_leak_bucket(&ts->cfg.buckets[i], delta_ns); in throttle_do_leak()
159 wait = throttle_compute_wait(&ts->cfg.buckets[index]); in throttle_compute_wait_for()
218 void throttle_config_init(ThrottleConfig *cfg) in throttle_config_init() argument
221 memset(cfg, 0, sizeof(*cfg)); in throttle_config_init()
223 cfg->buckets[i].burst_length = 1; in throttle_config_init()
231 throttle_config_init(&ts->cfg); in throttle_init()
298 bool throttle_enabled(ThrottleConfig *cfg) in throttle_enabled() argument
303 if (cfg->buckets[i].avg > 0) { in throttle_enabled()
316 bool throttle_is_valid(ThrottleConfig *cfg, Error **errp) in throttle_is_valid() argument
322 bps_flag = cfg->buckets[THROTTLE_BPS_TOTAL].avg && in throttle_is_valid()
[all …]
/openbmc/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_cfg.c142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
173 if (cfg->w[i].id == wid) in wilc_wlan_parse_response_frame()
174 cfg->w[i].val = get_unaligned_le32(&info[4]); in wilc_wlan_parse_response_frame()
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_fb.c105 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
108 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
116 writel(cfg, &reg->dualrgb); in exynos_fimd_set_dualrgb()
123 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
126 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
128 writel(cfg, &reg->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
135 unsigned int cfg = 0; in exynos_fimd_set_par() local
138 cfg = readl((unsigned int)&reg->wincon0 + in exynos_fimd_set_par()
141 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
[all …]
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_gen5.c40 static int get_errata_rows(const struct socfpga_sdram_config *cfg) in get_errata_rows() argument
46 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in get_errata_rows()
49 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> in get_errata_rows()
52 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> in get_errata_rows()
55 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> in get_errata_rows()
266 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) in sdr_get_ctrlcfg() argument
269 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in sdr_get_ctrlcfg()
272 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> in sdr_get_ctrlcfg()
275 u32 ctrl_cfg = cfg->ctrl_cfg; in sdr_get_ctrlcfg()
304 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) in sdr_get_addr_rw() argument
[all …]

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