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Searched refs:cacheline_size (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/tools/perf/util/
H A Dcacheline.h7 int __pure cacheline_size(void);
16 u64 size = cacheline_size(); in cl_address()
27 u64 size = cacheline_size(); in cl_offset()
H A Dcacheline.c17 int cacheline_size(void) in cacheline_size() function
H A Dsort.c3247 if (sd->entry == &sort_mem_dcacheline && cacheline_size() == 0) in sort_dimension__add()
3293 if (!cacheline_size() && !strncasecmp(tok, "dcacheline", strlen(tok))) in setup_sort_list()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/libhugetlbfs/files/
H A D0008-alloc.c-Avoid-sysconf-_SC_LEVEL2_CACHE_LINESIZE-on-l.patch42 if (cacheline_size == 0) {
43 - cacheline_size = sysconf(_SC_LEVEL2_CACHE_LINESIZE);
44 + cacheline_size = get_cacheline_size();
/openbmc/u-boot/drivers/usb/host/
H A Dxhci-mem.c192 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); in xhci_malloc() local
194 ptr = memalign(cacheline_size, ALIGN(size, cacheline_size)); in xhci_malloc()
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.h99 uint32_t cacheline_size; member
H A Dkfd_crat.c1107 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
H A Dkfd_topology.c357 cache->cacheline_size); in kfd_cache_show()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c355 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
363 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
371 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
379 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
387 .cacheline_size = I915_FIFO_LINE_SIZE,
395 .cacheline_size = I915_FIFO_LINE_SIZE,
403 .cacheline_size = I915_FIFO_LINE_SIZE,
411 .cacheline_size = I830_FIFO_LINE_SIZE,
419 .cacheline_size = I830_FIFO_LINE_SIZE,
427 .cacheline_size = I830_FIFO_LINE_SIZE,
[all …]
H A Dintel_display_types.h1572 u8 cacheline_size; member
/openbmc/linux/drivers/scsi/
H A Dmyrb.h297 unsigned short cacheline_size; /* Bytes 104-105 */ member
H A Dmyrs.h413 enum myrs_cacheline_size cacheline_size; /* Byte 7 */ member
H A Dmyrs.c1575 if (ldev_info->cacheline_size) { in myrs_mode_sense()
1577 put_unaligned_be16(1 << ldev_info->cacheline_size, in myrs_mode_sense()
/openbmc/linux/drivers/pci/
H A Dpci.c4561 u8 cacheline_size; in pci_set_cacheline_size() local
4568 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4569 if (cacheline_size >= pci_cache_line_size && in pci_set_cacheline_size()
4570 (cacheline_size % pci_cache_line_size) == 0) in pci_set_cacheline_size()
4576 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4577 if (cacheline_size == pci_cache_line_size) in pci_set_cacheline_size()
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c17030 int cacheline_size; in tg3_calc_dma_bndry() local
17036 cacheline_size = 1024; in tg3_calc_dma_bndry()
17038 cacheline_size = (int) byte * 4; in tg3_calc_dma_bndry()
17078 switch (cacheline_size) { in tg3_calc_dma_bndry()
17103 switch (cacheline_size) { in tg3_calc_dma_bndry()
17120 switch (cacheline_size) { in tg3_calc_dma_bndry()