| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PB | 43 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
44 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
45 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
46 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
47 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
49 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
| H A D | README.P1010RDB-PA | 61 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
62 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
63 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
64 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
65 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
67 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
| /openbmc/linux/Documentation/devicetree/bindings/pmem/ |
| H A D | pmem-region.txt | 6 a) Usable as main system memory (i.e. cacheable), and
25 (i.e cacheable).
|
| /openbmc/u-boot/board/renesas/sh7785lcr/ |
| H A D | README.sh7785lcr | 59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
65 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
|
| /openbmc/qemu/docs/specs/ |
| H A D | ppc-spapr-hcalls.rst | 53 PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or
54 non-cacheable accesses to any guest physical addresses that the
|
| H A D | vmgenid.rst | 45 cacheable.)
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| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | aliasing.rst | 19 WB Write-back (cacheable)
30 page with both a cacheable mapping and an uncacheable mapping[1].
71 means that to avoid attribute aliasing, Linux can create a cacheable
72 identity mapping only when the entire granule supports cacheable
|
| /openbmc/linux/arch/arm/mm/ |
| H A D | proc-arm946.S | 352 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
353 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
|
| H A D | proc-arm740.S | 97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
|
| H A D | proc-arm940.S | 308 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
|
| H A D | Kconfig | 1042 PL310 treats a cacheable write transaction during a Clean &
1064 not automatically drain. This can cause normal, non-cacheable
1118 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
|
| /openbmc/qemu/include/hw/acpi/ |
| H A D | aml-build.h | 370 AmlMaxFixed max_fixed, AmlCacheable cacheable,
376 AmlMaxFixed max_fixed, AmlCacheable cacheable,
|
| /openbmc/qemu/target/ppc/translate/ |
| H A D | misc-impl.c.inc | 121 * cacheable accesses. TCG_BAR_SC is required to provide this
|
| /openbmc/linux/arch/sparc/mm/ |
| H A D | viking.S | 96 mov 0x10, %g2 ! set cacheable bit
|
| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | README | 106 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
|
| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | README | 103 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
|
| /openbmc/qemu/hw/acpi/ |
| H A D | aml-build.c | 1499 AmlMaxFixed max_fixed, AmlCacheable cacheable, in aml_dword_memory() argument
1505 uint8_t flags = read_and_write | (cacheable << 1); in aml_dword_memory()
1519 AmlMaxFixed max_fixed, AmlCacheable cacheable, in aml_qword_memory() argument
1525 uint8_t flags = read_and_write | (cacheable << 1); in aml_qword_memory()
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3128.dtsi | 358 map-cacheable;
|
| /openbmc/linux/Documentation/admin-guide/cifs/ |
| H A D | usage.rst | 654 check to see whether a file is cacheable. CIFS has no way
656 is cacheable (oplocked). Unfortunately, even if a file
657 is not oplocked, it could still be cacheable (ie cifs client
|
| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | booting.rst | 51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | device-io.rst | 413 it as cacheable, see Documentation/arch/x86/pat.rst.
|
| /openbmc/linux/Documentation/admin-guide/hw-vuln/ |
| H A D | l1tf.rst | 81 marked present, never point to cacheable physical memory space.
|
| /openbmc/linux/arch/arm64/ |
| H A D | Kconfig | 716 address for a cacheable mapping of a location is being
766 non-cacheable memory attributes. The workaround depends on a firmware
|
| /openbmc/u-boot/doc/ |
| H A D | README.x86 | 564 tell the CPU whether memory is cacheable and if so the cache write
|