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Searched refs:__raw_writel (Results 1 – 25 of 514) sorted by relevance

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/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); in sdram_init()
[all …]
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
37 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); in sdram_init()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
47 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); in ddr3_init_ddrphy()
50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); in ddr3_init_ddrphy()
51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
[all …]
/openbmc/linux/arch/mips/alchemy/common/
H A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
H A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
141 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
150 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
H A Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
58 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift, in txx9tmr_set_state_periodic()
[all …]
/openbmc/linux/arch/arm/mach-mmp/
H A Dtime.c50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
75 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
92 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
103 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
108 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
121 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_shutdown()
153 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ in timer_config()
[all …]
/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/openbmc/u-boot/cmd/
H A Dtsi148.c83 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); in tsi148_init()
84 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); in tsi148_init()
88 __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); in tsi148_init()
101 __raw_writel(htonl(0x00000000), &dev->uregs->inten); in tsi148_init()
103 __raw_writel(htonl(0x00000000), &dev->uregs->inteo); in tsi148_init()
106 __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc); in tsi148_init()
108 __raw_writel(htonl(0x00000000), &dev->uregs->intm1); in tsi148_init()
109 __raw_writel(htonl(0x00000000), &dev->uregs->intm2); in tsi148_init()
114 __raw_writel(val, &dev->uregs->vstat); in tsi148_init()
157 __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal); in tsi148_pci_slave_window()
[all …]
/openbmc/u-boot/drivers/video/
H A Dipu_disp.c68 __raw_writel(0x2, DMFC_IC_CTRL); in ipu_dmfc_init()
131 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); in ipu_dmfc_init()
132 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); in ipu_dmfc_init()
133 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); in ipu_dmfc_init()
135 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); in ipu_dmfc_init()
176 __raw_writel(dmfc_gen1, DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
186 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
197 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
199 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); in ipu_di_data_pin_config()
222 __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); in ipu_di_sync_config()
[all …]
/openbmc/u-boot/drivers/dma/
H A Dti-edma3.c60 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
62 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH); in qedma3_start()
69 __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum)); in qedma3_start()
72 __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR); in qedma3_start()
73 __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR); in qedma3_start()
76 __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR); in qedma3_start()
107 __raw_writel(opt, &rg->opt); in edma3_set_dest()
108 __raw_writel(dst, &rg->dst); in edma3_set_dest()
133 __raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16), in edma3_set_dest_index()
135 __raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16), in edma3_set_dest_index()
[all …]
/openbmc/linux/arch/mips/pci/
H A Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
247 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
261 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
266 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
284 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
261 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/openbmc/linux/sound/soc/au1x/
H A Dpsc-ac97.c78 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
85 __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), in au1xpsc_ac97_read()
98 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
118 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
125 __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), in au1xpsc_ac97_write()
136 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
148 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
151 __raw_writel(0, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
161 __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); in au1xpsc_ac97_cold_reset()
163 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); in au1xpsc_ac97_cold_reset()
[all …]
H A Dpsc-i2s.c149 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
159 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
161 __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
173 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
174 __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
194 __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
196 __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
205 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
217 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_stop()
228 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_stop()
[all …]
/openbmc/linux/arch/mips/loongson32/common/
H A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
185 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
193 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
195 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); in mcf_pci_init()
[all …]
/openbmc/u-boot/board/mpr2/
H A Dmpr2.c26 __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ in board_init()
27 __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ in board_init()
30 __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
31 __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
34 __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
35 __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
38 __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
39 __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in board_init()
42 __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
43 __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ in board_init()
/openbmc/linux/arch/arm/mach-pxa/
H A Dsmemc.c37 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
38 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
39 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
40 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
44 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
46 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
65 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/openbmc/linux/arch/sh/mm/
H A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
35 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
112 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
115 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
116 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
/openbmc/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000_dma.h160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
177 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
242 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); in init_dma()
248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
249 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
307 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); in set_dma_fifo_addr()
[all …]
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dserial.c110 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
117 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
118 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
123 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
127 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
131 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
132 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
136 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
142 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
147 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/openbmc/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c41 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, in dram_init()
43 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, in dram_init()
50 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
51 __raw_writel(0x56570000, &sdp->cfg2); in dram_init()
53 __raw_writel(0xE1462C02, &sdp->ctrl); in dram_init()
56 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
58 __raw_writel(0xE1462C04, &sdp->ctrl); in dram_init()
60 __raw_writel(0x008D0000, &sdp->mode); in dram_init()
62 __raw_writel(0x80010000, &sdp->mode); in dram_init()
69 __raw_writel(0x71462C00, &sdp->ctrl); in dram_init()

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