Searched refs:XI0 (Results 1 – 3 of 3) sorted by relevance
72 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; in r4k_fill_tlb()120 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; in r4k_helper_tlbwi() local136 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; in r4k_helper_tlbwi()151 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || in r4k_helper_tlbwi()264 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | in r4k_helper_tlbr()421 if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { in r4k_map_address()433 if (!(n ? tlb->XI1 : tlb->XI0)) { in r4k_map_address()
158 v->XI0 = (flags >> 11) & 1; in get_tlb()176 (v->XI0 << 11) | in put_tlb()
133 unsigned int XI0:1; member