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Searched refs:VM_1_10_SV57 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmonitor.c180 case VM_1_10_SV57: in mem_info_svxx()
H A Dcpu.c359 return VM_1_10_SV57; in satp_mode_from_str()
399 case VM_1_10_SV57: in satp_mode_str()
456 VM_1_10_SV32 : VM_1_10_SV57); in riscv_max_cpu_init()
472 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); in rv64_base_cpu_init()
601 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); in rv128_base_cpu_init()
H A Dcpu_bits.h641 #define VM_1_10_SV57 10 macro
H A Dcpu_helper.c963 case VM_1_10_SV57: in get_physical_address()
H A Dcsr.c1464 [VM_1_10_SV57] = true
/openbmc/qemu/hw/riscv/
H A Dvirt-acpi-build.c346 if (satp_mode_max == VM_1_10_SV57) { in build_rhct()