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Searched refs:VM_1_10_SV48 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmonitor.c175 case VM_1_10_SV48: in mem_info_svxx()
H A Dcpu_bits.h640 #define VM_1_10_SV48 9 macro
H A Dcpu.c355 return VM_1_10_SV48; in satp_mode_from_str()
401 case VM_1_10_SV48: in satp_mode_str()
578 set_satp_mode_max_supported(cpu, VM_1_10_SV48); in rv64_veyron_v1_cpu_init()
H A Dcpu_helper.c961 case VM_1_10_SV48: in get_physical_address()
H A Dcsr.c1463 [VM_1_10_SV48] = true,
/openbmc/qemu/hw/riscv/
H A Dvirt-acpi-build.c348 } else if (satp_mode_max == VM_1_10_SV48) { in build_rhct()