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Searched refs:VM_1_10_SV32 (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmonitor.c165 case VM_1_10_SV32: in mem_info_svxx()
H A Dcpu.c347 return VM_1_10_SV32; in satp_mode_from_str()
390 case VM_1_10_SV32: in satp_mode_str()
456 VM_1_10_SV32 : VM_1_10_SV57); in riscv_max_cpu_init()
634 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); in rv32_base_cpu_init()
645 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); in rv32_sifive_u_cpu_init()
H A Dcpu_bits.h638 #define VM_1_10_SV32 1 macro
H A Dcpu_helper.c957 case VM_1_10_SV32: in get_physical_address()
992 if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { in get_physical_address()
H A Dcsr.c1457 [VM_1_10_SV32] = true