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Searched refs:VAL (Results 1 – 25 of 87) sorted by relevance

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/openbmc/qemu/target/hexagon/
H A Dmacros.h43 #define SET_USR_FIELD(FIELD, VAL) \ argument
48 reg_field_info[FIELD].offset, (VAL)); \
52 reg_field_info[FIELD].offset, (VAL)); \
217 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) argument
220 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) argument
222 #define fLSBOLD(VAL) ((VAL) & 1) argument
232 #define fLSBOLDNOT(VAL) \ argument
234 tcg_gen_andi_tl(LSB, (VAL), 1); \
244 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) argument
249 #define fNEWREG(VAL) ((int32_t)(VAL)) argument
[all …]
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc19 #define fLSBOLD(VAL) (fGETBIT(0, VAL))
20 #define fSATH(VAL) fSATN(16, VAL)
21 #define fSATUH(VAL) fSATUN(16, VAL)
22 #define fVSATH(VAL) fVSATN(16, VAL)
23 #define fVSATUH(VAL) fVSATUN(16, VAL)
24 #define fSATUB(VAL) fSATUN(8, VAL)
25 #define fSATB(VAL) fSATN(8, VAL)
26 #define fVSATUB(VAL) fVSATUN(8, VAL)
27 #define fVSATB(VAL) fVSATN(8, VAL)
38 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dbrev.c59 #define BREV_STORE(SZ, PART, ADDR, VAL, INC) \ argument
64 : "r"(VAL), "r"(INC) \
67 #define BREV_STORE_b(ADDR, VAL, INC) \ argument
68 BREV_STORE(b, "", ADDR, VAL, INC)
69 #define BREV_STORE_h(ADDR, VAL, INC) \ argument
70 BREV_STORE(h, "", ADDR, VAL, INC)
71 #define BREV_STORE_f(ADDR, VAL, INC) \ argument
72 BREV_STORE(h, ".H", ADDR, VAL, INC)
73 #define BREV_STORE_w(ADDR, VAL, INC) \ argument
74 BREV_STORE(w, "", ADDR, VAL, INC)
[all …]
H A Dcirc.c137 #define CIRC_STORE_IMM(SIZE, PART, VAL, ADDR, START, LEN, INC) \ argument
144 : "r"(START), "r"(VAL), "r"(LEN) \
146 #define CIRC_STORE_IMM_b(VAL, ADDR, START, LEN, INC) \ argument
147 CIRC_STORE_IMM(b, "", VAL, ADDR, START, LEN, INC)
148 #define CIRC_STORE_IMM_h(VAL, ADDR, START, LEN, INC) \ argument
149 CIRC_STORE_IMM(h, "", VAL, ADDR, START, LEN, INC)
150 #define CIRC_STORE_IMM_f(VAL, ADDR, START, LEN, INC) \ argument
151 CIRC_STORE_IMM(h, ".H", VAL, ADDR, START, LEN, INC)
152 #define CIRC_STORE_IMM_w(VAL, ADDR, START, LEN, INC) \ argument
153 CIRC_STORE_IMM(w, "", VAL, ADDR, START, LEN, INC)
[all …]
H A Dv69_hvx.c28 #define fVROUND(VAL, SHAMT) \ argument
29 ((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
31 #define fVSATUB(VAL) \ argument
32 ((((VAL) & 0xffLL) == (VAL)) ? \
33 (VAL) : \
34 ((((int32_t)(VAL)) < 0) ? 0 : 0xff))
36 #define fVSATUH(VAL) \ argument
37 ((((VAL) & 0xffffLL) == (VAL)) ? \
38 (VAL) : \
39 ((((int32_t)(VAL)) < 0) ? 0 : 0xffff))
/openbmc/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c59 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
61 AARCH64_DBG_READ(N, REG, VAL); \
64 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
66 AARCH64_DBG_WRITE(N, REG, VAL); \
69 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
70 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
71 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
72 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
73 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dhw_breakpoint.c48 #define READ_WB_REG_CASE(OP2, M, VAL) \ argument
50 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
53 #define WRITE_WB_REG_CASE(OP2, M, VAL) \ argument
55 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
58 #define GEN_READ_WB_REG_CASES(OP2, VAL) \ argument
59 READ_WB_REG_CASE(OP2, 0, VAL); \
60 READ_WB_REG_CASE(OP2, 1, VAL); \
61 READ_WB_REG_CASE(OP2, 2, VAL); \
62 READ_WB_REG_CASE(OP2, 3, VAL); \
63 READ_WB_REG_CASE(OP2, 4, VAL); \
[all …]
/openbmc/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh324 VAL=${1#*-}
326 if [[ $VAL -eq 0 ]]
335 echo $VAL > $CPUFILE
378 VAL=${CMD#?}
379 case $VAL in
380 0) VAL=member
382 1) VAL=root
384 2) VAL=isolated
387 echo "Invalid partition state - $VAL"
391 COMM="echo $VAL > $PFILE"
[all …]
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def112 ( (VAL) ? 0xff : 0x00),
118 ((VAL) & 1),
142 (!fLSBOLD(VAL)),
181 ({ ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
187 ({fSET_OVERFLOW(); ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
193 ({fSET_OVERFLOW(); ((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}),
199 ({((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}),
205 ((VAL) & ((1LL<<(N))-1)),
211 ((fZXTN(N,M,VAL) ^ (1LL<<((N)-1))) - (1LL<<((N)-1))),
217 ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATVALN(N,VAL)),
[all …]
/openbmc/linux/arch/loongarch/kernel/
H A Dhw_breakpoint.c36 #define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \ argument
38 LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \
41 #define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \ argument
43 LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \
46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \ argument
47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dbarrier.h196 __unqual_scalar_typeof(*ptr) VAL; \
198 VAL = READ_ONCE(*__PTR); \
201 __cmpwait_relaxed(__PTR, VAL); \
203 (typeof(*ptr))VAL; \
209 __unqual_scalar_typeof(*ptr) VAL; \
211 VAL = smp_load_acquire(__PTR); \
214 __cmpwait_relaxed(__PTR, VAL); \
216 (typeof(*ptr))VAL; \
H A Dhw_breakpoint.h99 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
100 VAL = read_sysreg(dbg##REG##N##_el1);\
103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
104 write_sysreg(VAL, dbg##REG##N##_el1);\
/openbmc/linux/include/uapi/linux/
H A Dbtf.h92 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
93 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
94 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/openbmc/linux/tools/include/uapi/linux/
H A Dbtf.h92 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
93 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
94 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/openbmc/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ argument
60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ argument
68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h48 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
50 env->vtcm_log.data.ub[IDX] = (VAL); \
59 #define fNOTQ(VAL) \ argument
64 _ret.ud[_i_] = ~VAL.ud[_i_]; \
94 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
96 uint32_t __TMP = (VAL); \
100 #define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL) argument
339 #define fVNOROUND(VAL, SHAMT) VAL argument
340 #define fVNOSAT(VAL) VAL argument
341 #define fVROUND(VAL, SHAMT) \ argument
[all …]
/openbmc/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) argument
643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) argument
645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) argument
647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) argument
648 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) argument
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/openbmc/linux/drivers/watchdog/
H A Dit87_wdt.c42 #define VAL 0x2f macro
132 outb(0x02, VAL); in superio_exit()
139 outb(ldn, VAL); in superio_select()
145 return inb(VAL); in superio_inb()
151 outb(val, VAL); in superio_outb()
158 val = inb(VAL) << 8; in superio_inw()
160 val |= inb(VAL); in superio_inw()
H A Dit8712f_wdt.c57 #define VAL 0x2f /* The value to read/write */ macro
95 return inb(VAL); in superio_inb()
101 outb(val, VAL); in superio_outb()
108 val = inb(VAL) << 8; in superio_inw()
110 val |= inb(VAL); in superio_inw()
117 outb(ldn, VAL); in superio_select()
138 outb(0x02, VAL); in superio_exit()
/openbmc/openbmc/poky/scripts/
H A Doe-git-proxy66 VAL=0
68 VAL=$(($VAL+$(($B<<$SHIFT))))
71 echo "$VAL"
/openbmc/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h950 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) argument
951 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) argument
952 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) argument
953 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) argument
954 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) argument
955 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) argument
956 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) argument
991 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/openbmc/linux/arch/arm/include/asm/
H A Dhw_breakpoint.h109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
110 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
114 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
/openbmc/linux/tools/testing/selftests/ntb/
H A Dntb_test.sh266 VAL=$RANDOM
267 write_file "$VAL" "$LOC/spad$i"
270 if [[ "$VAL" -ne "$RVAL" ]]; then
271 echo "Scratchpad $i value $RVAL doesn't match $VAL" >&2
300 VAL=$RANDOM
301 write_file "$VAL" "$LOC/msg$i"
304 if [[ "$VAL" -ne "${RVAL%%<-*}" ]]; then
305 echo "Message $i value $RVAL doesn't match $VAL" >&2
/openbmc/linux/kernel/locking/
H A Dqrwlock.c33 atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); in queued_read_lock_slowpath()
51 atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); in queued_read_lock_slowpath()
85 cnts = atomic_cond_read_relaxed(&lock->cnts, VAL == _QW_WAITING); in queued_write_lock_slowpath()
/openbmc/linux/drivers/gpio/
H A Dgpio-it87.c38 #define VAL 0x2f macro
95 outb(0x02, VAL); in superio_exit()
102 outb(ldn, VAL); in superio_select()
108 return inb(VAL); in superio_inb()
114 outb(val, VAL); in superio_outb()
122 val = inb(VAL) << 8; in superio_inw()
124 val |= inb(VAL); in superio_inw()

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