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Searched refs:TYPE6_LOAD (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Ddebug.h92 #define TYPE6_LOAD BIT(0) macro
H A Ddebug.c561 bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); in type6_breakpoint_enabled()
594 TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); in type6_mcontrol6_validate()
616 if (ctrl & TYPE6_LOAD) { in type6_breakpoint_insert()
1030 if (ctrl & TYPE6_LOAD) { in riscv_cpu_debug_check_watchpoint()