| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | snps,arc-timer.txt | 4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-lpc18xx.c | 254 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
255 LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
256 LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
257 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
258 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
262 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
326 LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
327 LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
[all …]
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| /openbmc/qemu/hw/avr/ |
| H A D | atmega.c | 29 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5, enumerator
35 #define TIMER(n) (n + TIMER0)
73 [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
93 [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
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| /openbmc/linux/arch/arc/boot/dts/ |
| H A D | skeleton.dtsi | 30 /* TIMER0 with interrupt for clockevent */
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| H A D | skeleton_hs.dtsi | 25 /* TIMER0 with interrupt for clockevent */
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| H A D | skeleton_hs_idu.dtsi | 43 /* TIMER0 with interrupt for clockevent */
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| H A D | abilis_tb10x.dtsi | 26 /* TIMER0 with interrupt for clockevent */
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| H A D | hsdk.dts | 95 /* TIMER0 with interrupt for clockevent */
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | brcm,bcm2835-armctrl-ic.txt | 45 0: TIMER0
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| /openbmc/linux/drivers/clocksource/ |
| H A D | Kconfig | 180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
181 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
291 TIMER0 serves as clockevent while TIMER1 provides clocksource.
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| /openbmc/linux/arch/arm/boot/dts/arm/ |
| H A D | integratorcp.dts | 149 /* TIMER0 runs directly on the 25MHz chrystal */
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| /openbmc/linux/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 266 LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH),
1257 LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
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| /openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| H A D | reg.h | 224 #define TIMER0 0x02E4 macro
|