Searched refs:TILE_SPLIT (Results 1 – 16 of 16) sorted by relevance
81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v6_0_tiling_mode_table_init()416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v6_0_tiling_mode_table_init()424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()436 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v6_0_tiling_mode_table_init()451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | in gfx_v6_0_tiling_mode_table_init()471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v6_0_tiling_mode_table_init()[all …]
70 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) macro2094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()2102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v8_0_tiling_mode_table_init()2106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v8_0_tiling_mode_table_init()2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1025 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in gfx_v7_0_tiling_mode_table_init()1029 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in gfx_v7_0_tiling_mode_table_init()1033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | in gfx_v7_0_tiling_mode_table_init()1038 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1045 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1046 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1060 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1076 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1096 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
191 # define TILE_SPLIT(x) ((x) << 11) macro
1134 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1195 # define TILE_SPLIT(x) ((x) << 11) macro
1944 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1913 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1988 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2038 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2527 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2536 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | in si_tiling_mode_table_init()2545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | in si_tiling_mode_table_init()2554 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2563 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2572 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2581 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2590 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2599 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()[all …]
2360 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2372 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); in cik_tiling_mode_table_init()2376 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2383 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()2387 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2503 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2507 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); in cik_tiling_mode_table_init()2511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
191 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_gfx8_tiling_info_from_flags()
1730 typedef enum TILE_SPLIT { enum1738 } TILE_SPLIT; typedef