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Searched refs:TCG_TARGET_NB_REGS (Results 1 – 24 of 24) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
H A Dtcg-target.h123 #define TCG_TARGET_NB_REGS 16 macro
H A Dtcg-target.c.inc212 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
933 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
935 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
H A Dtcg-target.c.inc29 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h75 #define TCG_TARGET_NB_REGS 32 macro
H A Dtcg-target.c.inc39 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h29 #define TCG_TARGET_NB_REGS 32 macro
H A Dtcg-target.c.inc34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h31 #define TCG_TARGET_NB_REGS 32 macro
H A Dtcg-target.c.inc40 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
875 #define SETCOND_INV TCG_TARGET_NB_REGS
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h35 #define TCG_TARGET_NB_REGS 64 macro
H A Dtcg-target.c.inc36 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
559 #define SETCOND_INV TCG_TARGET_NB_REGS
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h50 #define TCG_TARGET_NB_REGS 64 macro
H A Dtcg-target.c.inc23 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
/openbmc/qemu/include/tcg/
H A Dtcg.h59 #if TCG_TARGET_NB_REGS <= 32
61 #elif TCG_TARGET_NB_REGS <= 64
545 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h32 #define TCG_TARGET_NB_REGS 64 macro
H A Dtcg-target.c.inc115 static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h52 #define TCG_TARGET_NB_REGS 64 macro
H A Dtcg-target.c.inc326 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h31 #define TCG_TARGET_NB_REGS 64 macro
H A Dtcg-target.c.inc34 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
1217 #define SETCOND_INV TCG_TARGET_NB_REGS
/openbmc/qemu/tcg/
H A Dtci.c364 tcg_target_ulong regs[TCG_TARGET_NB_REGS]; in tcg_qemu_tb_exec()
1030 static const char regs[TCG_TARGET_NB_REGS][4] = { in str_r()
1038 assert((unsigned)r < TCG_TARGET_NB_REGS); in str_r()
H A Dtcg.c2546 if (TCG_TARGET_NB_REGS <= 32) { in tcg_regset_first()
2872 } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { in tcg_dump_ops()
2879 } else if (TCG_TARGET_NB_REGS <= 32) { in tcg_dump_ops()
4940 ts->reg < TCG_TARGET_NB_REGS - 1 && in tcg_reg_alloc_op()
5066 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { in tcg_reg_alloc_op()
5404 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { in tcg_reg_alloc_call()