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Searched refs:TCG_TARGET_HAS_rot_i32 (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h70 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h104 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h87 #define TCG_TARGET_HAS_rot_i32 0 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h164 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h104 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h78 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h80 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h77 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h76 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h131 #define TCG_TARGET_HAS_rot_i32 1 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h77 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
78 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
/openbmc/qemu/tcg/
H A Dtcg-op.c816 if (TCG_TARGET_HAS_rot_i32) { in tcg_gen_rotl_i32()
838 } else if (TCG_TARGET_HAS_rot_i32) { in tcg_gen_rotli_i32()
854 if (TCG_TARGET_HAS_rot_i32) { in tcg_gen_rotr_i32()
H A Dtci.c642 #if TCG_TARGET_HAS_rot_i32 in tcg_qemu_tb_exec()
H A Dtcg.c2008 return TCG_TARGET_HAS_rot_i32; in tcg_op_supported()