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Searched refs:TCG_TARGET_HAS_muls2_i32 (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h72 #define TCG_TARGET_HAS_muls2_i32 1 macro
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h119 #define TCG_TARGET_HAS_muls2_i32 1 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h111 #define TCG_TARGET_HAS_muls2_i32 1 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h127 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h112 #define TCG_TARGET_HAS_muls2_i32 0 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h95 #define TCG_TARGET_HAS_muls2_i32 0 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h100 #define TCG_TARGET_HAS_muls2_i32 0 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h101 #define TCG_TARGET_HAS_muls2_i32 0 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h84 #define TCG_TARGET_HAS_muls2_i32 0 macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h155 #define TCG_TARGET_HAS_muls2_i32 1 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h89 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
/openbmc/qemu/tcg/
H A Dtci.c699 #if TCG_TARGET_HAS_muls2_i32 in tcg_qemu_tb_exec()
H A Dtcg-op.c1207 if (TCG_TARGET_HAS_muls2_i32) { in tcg_gen_muls2_i32()
H A Dtcg.c2024 return TCG_TARGET_HAS_muls2_i32; in tcg_op_supported()