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Searched refs:TCG_TARGET_HAS_ext8s_i32 (Results 1 – 16 of 16) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h53 #define TCG_TARGET_HAS_ext8s_i32 1 macro
H A Dtcg-target.c.inc551 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
/openbmc/qemu/tcg/arm/
H A Dtcg-target.h97 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h88 #define TCG_TARGET_HAS_ext8s_i32 0 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h162 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions macro
H A Dtcg-target.c.inc642 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h115 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h71 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h81 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h78 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h87 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h132 #define TCG_TARGET_HAS_ext8s_i32 1 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h96 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
/openbmc/qemu/tcg/
H A Dtcg-op.c1083 if (TCG_TARGET_HAS_ext8s_i32) { in tcg_gen_sextract_i32()
1099 if (TCG_TARGET_HAS_ext8s_i32) { in tcg_gen_sextract_i32()
1274 if (TCG_TARGET_HAS_ext8s_i32) { in tcg_gen_ext8s_i32()
H A Dtci.c706 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 in tcg_qemu_tb_exec()
H A Dtcg.c2030 return TCG_TARGET_HAS_ext8s_i32; in tcg_op_supported()