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Searched refs:TCG_TARGET_HAS_eqv_i64 (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h95 #define TCG_TARGET_HAS_eqv_i64 1 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h132 #define TCG_TARGET_HAS_eqv_i64 0 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h143 #define TCG_TARGET_HAS_eqv_i64 0 macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h157 #define TCG_TARGET_HAS_eqv_i64 0 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h116 #define TCG_TARGET_HAS_eqv_i64 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h124 #define TCG_TARGET_HAS_eqv_i64 1 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h121 #define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3) macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h128 #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h176 #define TCG_TARGET_HAS_eqv_i64 0 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h177 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
H A Dtcg.h86 #define TCG_TARGET_HAS_eqv_i64 0 macro
/openbmc/qemu/tcg/
H A Dtci.c570 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 in tcg_qemu_tb_exec()
H A Dtcg-op.c2400 } else if (TCG_TARGET_HAS_eqv_i64) { in tcg_gen_eqv_i64()
H A Dtcg.c2143 return TCG_TARGET_HAS_eqv_i64; in tcg_op_supported()