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Searched refs:TCG_TARGET_HAS_add2_i32 (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/tcg/tci/
H A Dtcg-target.h106 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.h108 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/mips/
H A Dtcg-target.h134 #define TCG_TARGET_HAS_add2_i32 0 macro
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.h109 #define TCG_TARGET_HAS_add2_i32 0 macro
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.h92 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.h106 #define TCG_TARGET_HAS_add2_i32 0 macro
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.h98 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.h81 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/i386/
H A Dtcg-target.h152 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/include/tcg/
H A Dtcg-opc.h86 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
H A Dtcg.h104 #define TCG_TARGET_HAS_add2_i32 1 macro
/openbmc/qemu/tcg/
H A Dtci.c676 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 in tcg_qemu_tb_exec()
H A Dtcg-op.c1150 if (TCG_TARGET_HAS_add2_i32) { in tcg_gen_add2_i32()
H A Dtcg.c2018 return TCG_TARGET_HAS_add2_i32; in tcg_op_supported()
/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c496 if (TCG_TARGET_HAS_add2_i32) { in gen_adc_CC()