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Searched refs:TCG_COND_LTU (Results 1 – 25 of 46) sorted by relevance

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/openbmc/qemu/include/tcg/
H A Dtcg-cond.h56 TCG_COND_LTU = 8 | 0 | 2 | 0, enumerator
/openbmc/qemu/target/arm/tcg/
H A Dgengvec64.c303 tcg_gen_movcond_i64(TCG_COND_LTU, tpos, tmp, a, max, tmp); in gen_usqadd_d()
307 tcg_gen_movcond_i64(TCG_COND_LTU, tneg, a, tneg, zero, tmp); in gen_usqadd_d()
H A Dgengvec.c1030 tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i32()
1031 tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i32()
1052 tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i64()
1053 tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i64()
1368 tcg_gen_movcond_i64(TCG_COND_LTU, res, t, a, in gen_uqadd_d()
1514 tcg_gen_movcond_i64(TCG_COND_LTU, res, a, b, tcg_constant_i64(0), t); in gen_uqsub_d()
1707 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i32()
1716 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i64()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_branch.c.inc79 TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)
H A Dtrans_vec.c.inc4631 TRANS(vslt_bu, LSX, do_cmp, MO_8, TCG_COND_LTU)
4632 TRANS(vslt_hu, LSX, do_cmp, MO_16, TCG_COND_LTU)
4633 TRANS(vslt_wu, LSX, do_cmp, MO_32, TCG_COND_LTU)
4634 TRANS(vslt_du, LSX, do_cmp, MO_64, TCG_COND_LTU)
4635 TRANS(vslti_bu, LSX, do_cmpi, MO_8, TCG_COND_LTU)
4636 TRANS(vslti_hu, LSX, do_cmpi, MO_16, TCG_COND_LTU)
4637 TRANS(vslti_wu, LSX, do_cmpi, MO_32, TCG_COND_LTU)
4638 TRANS(vslti_du, LSX, do_cmpi, MO_64, TCG_COND_LTU)
4647 TRANS(xvslt_bu, LASX, do_xcmp, MO_8, TCG_COND_LTU)
4648 TRANS(xvslt_hu, LASX, do_xcmp, MO_16, TCG_COND_LTU)
[all …]
H A Dtrans_arith.c.inc90 tcg_gen_setcond_tl(TCG_COND_LTU, dest, src1, src2);
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc619 [TCG_COND_LTU] = COND_CS,
732 case TCG_COND_LTU:
747 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
756 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU);
782 if (cond == TCG_COND_LTU) {
814 case TCG_COND_LTU:
878 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
/openbmc/qemu/target/openrisc/
H A Dtranslate.c241 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); in gen_sub()
372 tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); in gen_macu()
412 tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); in gen_msbu()
967 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, in trans_l_sfltu()
1033 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfltui()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc178 case TCG_COND_LTU:
189 tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl);
276 return gen_branch(ctx, a, TCG_COND_LTU);
512 tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
518 gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
H A Dtrans_rvm.c.inc42 tcg_gen_setcond_tl(TCG_COND_LTU, r3, tmph, r2);
/openbmc/qemu/tcg/
H A Doptimize.c627 case TCG_COND_LTU: in do_constant_folding_cond_32()
661 case TCG_COND_LTU: in do_constant_folding_cond_64()
684 case TCG_COND_LTU: in do_constant_folding_cond_eq()
729 case TCG_COND_LTU: in do_constant_folding_cond()
885 case TCG_COND_LTU: in do_constant_folding_cond2()
2134 case TCG_COND_LTU: in fold_setcond_zmask()
2160 case TCG_COND_LTU: in fold_setcond_zmask()
H A Dtci.c220 case TCG_COND_LTU: in tci_compare32()
268 case TCG_COND_LTU: in tci_compare64()
1053 [TCG_COND_LTU] = "ltu", in str_c()
H A Dtcg-op.c1401 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i32()
1411 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i32()
3023 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al); in tcg_gen_add2_i64()
3041 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl); in tcg_gen_sub2_i64()
3129 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i64()
3139 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i64()
H A Dtcg-op-gvec.c2268 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i32()
2275 tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i64()
2310 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i32()
2317 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i64()
3762 [TCG_COND_LTU] = ltu_fn, in tcg_gen_gvec_cmp()
3884 [TCG_COND_LTU] = ltu_fn, in tcg_gen_gvec_cmps()
/openbmc/qemu/accel/tcg/
H A Dplugin-gen.c145 return TCG_COND_LTU; in plugin_cond_to_tcgcond()
/openbmc/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc1334 tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
1339 tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
2238 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2240 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2242 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(16),
2245 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2247 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2249 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
2830 tcg_gen_cmp_vec(TCG_COND_LTU, vece, t, a, b);
2837 tcg_gen_setcond_i32(TCG_COND_LTU, t, a, b);
/openbmc/qemu/target/tricore/
H A Dtranslate.c572 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); in gen_maddu64_d()
3044 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, in gen_compute_branch()
3108 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
5081 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5109 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5128 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, in decode_rc_accumulator()
5153 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5187 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5211 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5670 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc598 cond = TCG_COND_LTU;
631 case TCG_COND_LTU:
723 [TCG_COND_LTU] = { OPC_BGTU, true },
1854 [TCG_COND_LTU] = {
1876 [TCG_COND_LTU] = {
2012 cond == TCG_COND_LTU) &&
/openbmc/qemu/target/m68k/
H A Dtranslate.c573 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); in gen_flush_flags()
1198 tcond = TCG_COND_LTU; in gen_cc_cond()
1835 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); in DISAS_INSN()
1838 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); in DISAS_INSN()
2281 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); in DISAS_INSN()
2290 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); in DISAS_INSN()
2964 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN()
2969 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN()
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc547 [TCG_COND_LTU] = JCC_JB,
1640 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2],
1664 case TCG_COND_LTU:
1665 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3],
1668 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2],
1672 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3],
1748 case TCG_COND_LTU:
1755 tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw);
3108 [TCG_COND_LTU] = NEED_UMAX | NEED_INV,
3167 [TCG_COND_LTU] = 1,
/openbmc/qemu/target/hexagon/idef-parser/
H A Didef-parser.y614 $$ = gen_bin_cmp(c, &@1, TCG_COND_LTU, &$1, &$3);
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc317 case TCG_COND_LTU:
732 [TCG_COND_LTU] = BC | BI(0, CR_LT) | BO_COND_TRUE,
748 [TCG_COND_LTU] = ISEL | BC_(0, CR_LT),
1836 case TCG_COND_LTU:
2055 case TCG_COND_LTU:
2183 [TCG_COND_LTU] = { CR_LT, CR_LT },
2232 case TCG_COND_LTU:
3786 case TCG_COND_LTU:
/openbmc/qemu/target/hexagon/
H A Dgen_tcg.h1060 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
1062 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc356 [TCG_COND_LTU] = { OPC_VMSLTU_VV, false },
376 [TCG_COND_LTU] = { OPC_VMSLEU_VI, 1, 16, true },
1194 [TCG_COND_LTU] = { OPC_BLTU, false },
1256 cond = TCG_COND_LTU;
1299 case TCG_COND_LTU:
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc425 [TCG_COND_LTU] = S390_CC_LT,
443 [TCG_COND_LTU] = S390_CC_NEVER,
593 case TCG_COND_LTU:
1336 case TCG_COND_LTU:
1384 case TCG_COND_LTU:
2873 case TCG_COND_LTU:

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