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Searched refs:TCG_COND_LT (Results 1 – 25 of 50) sorted by relevance

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/openbmc/qemu/include/tcg/
H A Dtcg-cond.h50 TCG_COND_LT = 0 | 0 | 2 | 0, enumerator
/openbmc/qemu/target/arm/tcg/
H A Dgengvec64.c310 tcg_gen_movcond_i64(TCG_COND_LT, res, b, zero, tneg, tpos); in gen_usqadd_d()
327 tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, b, z, t, u); in gen_usqadd_vec()
H A Dgengvec.c86 GEN_CMP0(gen_gvec_clt0, TCG_COND_LT) in GEN_CMP0()
1149 tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval); in gen_sshl_i32()
1172 tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval); in gen_sshl_i64()
1211 tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, zero, rval, lval); in gen_sshl_vec()
1214 tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, sgn, lval, rval); in gen_sshl_vec()
1449 tcg_gen_movcond_i64(TCG_COND_LT, res, t1, tcg_constant_i64(0), t2, t0); in gen_sqadd_d()
1594 tcg_gen_movcond_i64(TCG_COND_LT, res, t1, tcg_constant_i64(0), t2, t0); in gen_sqsub_d()
1650 tcg_gen_movcond_i32(TCG_COND_LT, d, a, b, d, t); in gen_sabd_i32()
1659 tcg_gen_movcond_i64(TCG_COND_LT, d, a, b, d, t); in gen_sabd_i64()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_branch.c.inc77 TRANS(blt, ALL, gen_rr_bc, TCG_COND_LT)
H A Dtrans_vec.c.inc3401 tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, a, zero, t1, b);
4623 TRANS(vslt_b, LSX, do_cmp, MO_8, TCG_COND_LT)
4624 TRANS(vslt_h, LSX, do_cmp, MO_16, TCG_COND_LT)
4625 TRANS(vslt_w, LSX, do_cmp, MO_32, TCG_COND_LT)
4626 TRANS(vslt_d, LSX, do_cmp, MO_64, TCG_COND_LT)
4627 TRANS(vslti_b, LSX, do_cmpi, MO_8, TCG_COND_LT)
4628 TRANS(vslti_h, LSX, do_cmpi, MO_16, TCG_COND_LT)
4629 TRANS(vslti_w, LSX, do_cmpi, MO_32, TCG_COND_LT)
4630 TRANS(vslti_d, LSX, do_cmpi, MO_64, TCG_COND_LT)
4639 TRANS(xvslt_b, LASX, do_xcmp, MO_8, TCG_COND_LT)
[all …]
H A Dtrans_arith.c.inc85 tcg_gen_setcond_tl(TCG_COND_LT, dest, src1, src2);
/openbmc/qemu/target/mips/tcg/
H A Dmxu_translate.c2414 tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1); in gen_mxu_q8slt()
2452 tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32SLT()
2493 tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1); in gen_mxu_D16SLT()
2497 tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1); in gen_mxu_D16SLT()
3833 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi); in gen_mxu_Q16SAT()
3845 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo); in gen_mxu_Q16SAT()
3869 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi); in gen_mxu_Q16SAT()
3881 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo); in gen_mxu_Q16SAT()
3934 tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_hi_lt); in gen_mxu_q16scop()
3947 tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_lo_lt); in gen_mxu_q16scop()
[all …]
/openbmc/qemu/target/alpha/
H A Dtranslate.c513 case TCG_COND_LT: in gen_fold_mzero()
1599 tcg_gen_setcond_i64(TCG_COND_LT, vc, va, vb); in translate_one()
1707 tcg_gen_movcond_i64(TCG_COND_LT, vc, va, load_zero(ctx), in translate_one()
2256 gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc); in translate_one()
2795 ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21); in translate_one()
2827 ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21); in translate_one()
/openbmc/qemu/target/tricore/
H A Dtranslate.c507 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_madd32_d()
1007 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_madd32_q()
1217 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); in gen_msub32_d()
1751 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); in gen_msub32_q()
2518 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); in gen_shaci()
2978 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); in gen_compute_branch()
3041 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); in gen_compute_branch()
3105 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], in gen_compute_branch()
3203 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_src_opc()
3275 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], in decode_srr_opc()
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc600 cond = TCG_COND_LT;
630 case TCG_COND_LT:
634 if (cond == TCG_COND_LT) {
644 if (cond == TCG_COND_LT) {
719 [TCG_COND_LT] = { OPC_BGT, true },
1850 [TCG_COND_LT] = {
1872 [TCG_COND_LT] = {
2006 cond == TCG_COND_LT) &&
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc164 case TCG_COND_LT:
266 return gen_branch(ctx, a, TCG_COND_LT);
501 tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
507 gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
/openbmc/qemu/tcg/
H A Dtci.c208 case TCG_COND_LT: in tci_compare32()
256 case TCG_COND_LT: in tci_compare64()
1049 [TCG_COND_LT] = "lt", in str_c()
H A Dtcg-op-vec.c433 tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, in tcg_gen_abs_vec()
652 do_minmax(vece, r, a, b, INDEX_op_smin_vec, TCG_COND_LT); in tcg_gen_smin_vec()
H A Doptimize.c619 case TCG_COND_LT: in do_constant_folding_cond_32()
653 case TCG_COND_LT: in do_constant_folding_cond_64()
685 case TCG_COND_LT: in do_constant_folding_cond_eq()
1372 case TCG_COND_LT: in fold_brcond2()
2351 case TCG_COND_LT: in fold_setcond2()
H A Dtcg-op.c1396 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); in tcg_gen_smin_i32()
1406 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); in tcg_gen_smax_i32()
3124 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); in tcg_gen_smin_i64()
3134 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); in tcg_gen_smax_i64()
/openbmc/qemu/accel/tcg/
H A Dtranslator.c75 tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); in gen_tb_start()
/openbmc/qemu/target/hexagon/
H A Dgenptr.c1023 tcg_gen_movcond_tl(TCG_COND_LT, satval, src, tcg_constant_tl(0), min, max); in gen_shl_sat()
1367 tcg_gen_movcond_tl(TCG_COND_LT, tmp, source, zero, zero, tmp); in gen_satu_i32()
1404 tcg_gen_movcond_i64(TCG_COND_LT, tmp, source, zero, zero, tmp); in gen_satu_i64()
H A Dgen_tcg.h1033 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
1035 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
/openbmc/qemu/target/rx/
H A Dtranslate.c282 dc->cond = TCG_COND_LT; in psw_cond()
288 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; in psw_cond()
300 dc->cond = TCG_COND_LT; in psw_cond()
1816 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc311 case TCG_COND_LT:
728 [TCG_COND_LT] = BC | BI(0, CR_LT) | BO_COND_TRUE,
744 [TCG_COND_LT] = ISEL | BC_(0, CR_LT),
1821 case TCG_COND_LT:
1974 case TCG_COND_LT:
2054 case TCG_COND_LT:
2179 [TCG_COND_LT ] = { CR_LT, CR_LT },
2228 case TCG_COND_LT:
3785 case TCG_COND_LT:
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc352 [TCG_COND_LT] = { OPC_VMSLT_VV, false },
372 [TCG_COND_LT] = { OPC_VMSLE_VI, -15, 16, true },
1190 [TCG_COND_LT] = { OPC_BLT, false },
1258 cond = TCG_COND_LT;
1291 case TCG_COND_LT:
1354 case TCG_COND_LT:
/openbmc/qemu/target/hexagon/idef-parser/
H A Didef-parser.y616 $$ = gen_bin_cmp(c, &@1, TCG_COND_LT, &$1, &$3);
/openbmc/qemu/target/m68k/
H A Dtranslate.c1213 tcond = TCG_COND_LT; in gen_cc_cond()
1257 tcond = TCG_COND_LT; in gen_cc_cond()
1322 tcond = TCG_COND_LT; in gen_cc_cond()
1327 tcond = TCG_COND_LT; in gen_cc_cond()
1333 tcond = TCG_COND_LT; in gen_cc_cond()
1342 tcond = TCG_COND_LT; in gen_cc_cond()
3636 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); in rotate_x()
/openbmc/qemu/target/xtensa/
H A Dtranslate.c2873 .par = (const uint32_t[]){TCG_COND_LT},
2880 .par = (const uint32_t[]){TCG_COND_LT},
2901 .par = (const uint32_t[]){TCG_COND_LT},
3282 .par = (const uint32_t[]){TCG_COND_LT},
4517 .par = (const uint32_t[]){TCG_COND_LT},
6700 .par = (const uint32_t[]){TCG_COND_LT},
7378 .par = (const uint32_t[]){TCG_COND_LT},
7383 .par = (const uint32_t[]){TCG_COND_LT},
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc543 [TCG_COND_LT] = JCC_JL,
1636 case TCG_COND_LT:
1637 tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3],
1644 tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3],
1774 case TCG_COND_LT:
3103 [TCG_COND_LT] = NEED_SWAP,
3166 [TCG_COND_LT] = 1,
3212 && cond != TCG_COND_LT

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