| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp-pcie-msm8996.c | 25 #define SW_RESET BIT(0) macro
349 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); in qmp_pcie_msm8996_serdes_init()
433 SW_RESET); in qmp_pcie_msm8996_com_exit()
504 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_msm8996_power_on()
536 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_msm8996_power_off()
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| H A D | phy-qcom-qmp-usb-legacy.c | 29 #define SW_RESET BIT(0) macro
794 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); in qmp_usb_legacy_init_dp_com()
887 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_legacy_power_on()
916 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_legacy_power_off()
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| H A D | phy-qcom-qmp-ufs.c | 33 #define SW_RESET BIT(0) macro
1332 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_ufs_power_on()
1355 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_ufs_power_off()
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| H A D | phy-qcom-qmp-usb.c | 28 #define SW_RESET BIT(0) macro
1747 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_power_on()
1776 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_power_off()
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| H A D | phy-qcom-qmp-combo.c | 35 #define SW_RESET BIT(0) macro
2444 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); in qmp_combo_com_init()
2591 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_on()
2620 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_off()
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| H A D | phy-qcom-qmp-pcie.c | 36 #define SW_RESET BIT(0) macro
3262 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
3295 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | gdsc.h | 64 #define SW_RESET BIT(3) macro
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| H A D | gpucc-sdm660.c | 255 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| H A D | gpucc-msm8998.c | 271 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| H A D | gpucc-sm6375.c | 380 .flags = CLAMP_IO | SW_RESET | AON_RESET,
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| H A D | gpucc-sm6115.c | 417 .flags = CLAMP_IO | SW_RESET | VOTABLE,
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| H A D | gdsc.c | 267 if (sc->flags & SW_RESET) { in gdsc_enable()
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| H A D | gpucc-sm8450.c | 664 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | mv88e6352.c | 29 #define SW_RESET 0x8000 macro
214 reg = SW_RESET | PPU_ENABLE | 0x0400; in mv88e_sw_reset()
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| /openbmc/linux/drivers/watchdog/ |
| H A D | asm9260_wdt.c | 50 SW_RESET, enumerator
277 priv->mode = SW_RESET; in asm9260_wdt_get_dt_mode()
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| /openbmc/linux/sound/soc/tegra/ |
| H A D | tegra210_admaif.h | 67 #define SW_RESET 1 macro
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| H A D | tegra210_admaif.c | 384 regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET); in tegra_admaif_stop()
388 !(val & SW_RESET_MASK & SW_RESET), in tegra_admaif_stop()
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| /openbmc/u-boot/include/net/pfe_eth/pfe/cbus/ |
| H A D | tmu_csr.h | 126 #define SW_RESET BIT(0) /* Global software reset */ macro
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| /openbmc/linux/drivers/net/dsa/microchip/ |
| H A D | lan937x_reg.h | 45 #define SW_RESET BIT(1) macro
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| H A D | lan937x_main.c | 147 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); in lan937x_reset_switch()
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| H A D | ksz9477_reg.h | 167 #define SW_RESET BIT(1) macro
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| H A D | ksz9477.c | 170 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); in ksz9477_reset_switch()
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qp-prtwd3.dts | 277 "", "", "", "", "", "SW_RESET", "", "",
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| /openbmc/linux/drivers/net/wireless/intel/ipw2x00/ |
| H A D | ipw2100.h | 301 SW_RESET, enumerator
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| /openbmc/u-boot/drivers/net/pfe_eth/ |
| H A D | pfe_hw.c | 860 writel(SW_RESET, TMU_CTRL); in tmu_init()
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