| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | Kconfig | 3 bool "STM32MP1 DDR driver"
9 activate STM32MP1 DDR controller driver for STM32MP1 soc
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| /openbmc/u-boot/drivers/reset/ |
| H A D | stm32-reset.c | 39 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) in stm32_reset_assert()
56 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) in stm32_reset_deassert()
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller
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| /openbmc/u-boot/board/st/stm32mp1/ |
| H A D | MAINTAINERS | 1 STM32MP1 BOARD
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| H A D | README | 6 U-Boot on STMicroelectronics STM32MP1
56 All the STM32MP1 board supported by U-Boot use the same generic board
81 from SDK for STM32MP1, or any crosstoolchains from your distribution)
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp153c-dhcor-drc-compact.dts | 5 * DHCOR STM32MP1 variant:
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| H A D | stm32mp15xx-dhcom-drc02.dtsi | 128 * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
129 * however the STM32MP1 pinmux cannot map them to UART4 .
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| H A D | stm32mp157c-dhcom-pdk2.dts | 5 * DHCOM STM32MP1 variant:
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| H A D | stm32mp157c-dhcom-picoitx.dts | 5 * DHCOM STM32MP1 variant:
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| H A D | stm32mp153c-dhcom-drc02.dts | 5 * DHCOM STM32MP1 variant:
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| H A D | stm32mp157c-phycore-stm32mp1-3.dts | 16 model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
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| H A D | stm32mp157a-dhcor-avenger96.dts | 7 * DHCOR STM32MP1 variant:
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| H A D | stm32mp157a-icore-stm32mp1-ctouch2.dts | 16 model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
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| H A D | stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 16 model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
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| H A D | stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 16 model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame";
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| H A D | stm32mp157a-icore-stm32mp1-edimm2.2.dts | 16 model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
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| H A D | stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 16 model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
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| H A D | stm32mp157c-phycore-stm32mp15-som.dtsi | 92 label = "STM32MP1-PHYCORE";
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| /openbmc/u-boot/drivers/misc/ |
| H A D | stm32_rcc.c | 35 .soc = STM32MP1,
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| /openbmc/u-boot/include/ |
| H A D | stm32_rcc.h | 46 STM32MP1, enumerator
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| /openbmc/u-boot/drivers/clk/ |
| H A D | Kconfig | 94 bool "Enable RCC clock driver for STM32MP1"
99 manipulating STM32MP1's on-SoC clocks.
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| /openbmc/u-boot/arch/arm/mach-stm32mp/ |
| H A D | Kconfig | 38 target STMicroelectronics SOC STM32MP1 family
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| /openbmc/linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32mp1.txt | 1 STMicroelectronics STM32MP1 clock tree initialization
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| /openbmc/u-boot/drivers/power/pmic/ |
| H A D | Kconfig | 239 It is accessed via an I2C interface. The device is used with STM32MP1
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