Searched refs:SSSR_ROR (Results 1 – 10 of 10) sorted by relevance
29 if (status & SSSR_ROR) in ssp_interrupt()32 Ser4SSSR = SSSR_ROR; in ssp_interrupt()174 Ser4SSSR = SSSR_ROR; in ssp_restore_state()202 Ser4SSSR = SSSR_ROR; in ssp_init()
38 error = read_SSSR_bits(drv_data, drv_data->mask_sr) & SSSR_ROR; in pxa2xx_spi_dma_transfer_complete()120 if (status & SSSR_ROR) { in pxa2xx_spi_dma_transfer()
475 write_SSSR_CS(drv_data, SSSR_ROR); in pxa2xx_spi_flush()646 if (irq_status & SSSR_ROR) { in interrupt_transfer()1511 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()1519 | SSSR_ROR | SSSR_TUR; in pxa2xx_spi_probe()
75 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ macro
83 #define SSSR_ROR BIT(7) /* Receive FIFO Overrun */ macro
65 | SSSR_ROR /* ROR = 1; Clear ROR */
1398 #define SSSR_ROR (1 << 7) macro1405 level |= (s->sssr & SSSR_ROR); in strongarm_ssp_int_update()1525 s->sssr |= SSSR_ROR; in strongarm_ssp_write()
140 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; in pxa_ssp_resume()
809 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ macro
1089 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ macro