1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 251100cfcSAjay Bhargav /* 351100cfcSAjay Bhargav * (C) Copyright 2011 451100cfcSAjay Bhargav * eInfochips Ltd. <www.einfochips.com> 5c7c47ca2SAjay Bhargav * Written-by: Ajay Bhargav <contact@8051projects.net> 651100cfcSAjay Bhargav * 751100cfcSAjay Bhargav * (C) Copyright 2010 851100cfcSAjay Bhargav * Marvell Semiconductor <www.marvell.com> 951100cfcSAjay Bhargav */ 1051100cfcSAjay Bhargav 1151100cfcSAjay Bhargav #ifndef __ARMADA100_SPI_H_ 1251100cfcSAjay Bhargav #define __ARMADA100_SPI_H_ 1351100cfcSAjay Bhargav 1451100cfcSAjay Bhargav #include <asm/arch/armada100.h> 1551100cfcSAjay Bhargav 1651100cfcSAjay Bhargav #define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE 1751100cfcSAjay Bhargav #define SSP_REG_BASE(x) CAT_BASE_ADDR(x) 1851100cfcSAjay Bhargav 1951100cfcSAjay Bhargav /* 2051100cfcSAjay Bhargav * SSP Serial Port Registers 2151100cfcSAjay Bhargav * refer Appendix A.26 2251100cfcSAjay Bhargav */ 2351100cfcSAjay Bhargav struct ssp_reg { 2451100cfcSAjay Bhargav u32 sscr0; /* SSP Control Register 0 - 0x000 */ 2551100cfcSAjay Bhargav u32 sscr1; /* SSP Control Register 1 - 0x004 */ 2651100cfcSAjay Bhargav u32 sssr; /* SSP Status Register - 0x008 */ 2751100cfcSAjay Bhargav u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ 2851100cfcSAjay Bhargav u32 ssdr; /* SSP Data Register - 0x010 */ 2951100cfcSAjay Bhargav u32 pad1[5]; 3051100cfcSAjay Bhargav u32 ssto; /* SSP Timeout Register - 0x028 */ 3151100cfcSAjay Bhargav u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ 3251100cfcSAjay Bhargav u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ 3351100cfcSAjay Bhargav u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ 3451100cfcSAjay Bhargav u32 sstss; /* SSP Timeslot Status Register - 0x038 */ 3551100cfcSAjay Bhargav }; 3651100cfcSAjay Bhargav 3751100cfcSAjay Bhargav #define DEFAULT_WORD_LEN 8 3851100cfcSAjay Bhargav #define SSP_FLUSH_NUM 0x2000 3951100cfcSAjay Bhargav #define RX_THRESH_DEF 8 4051100cfcSAjay Bhargav #define TX_THRESH_DEF 8 4151100cfcSAjay Bhargav #define TIMEOUT_DEF 1000 4251100cfcSAjay Bhargav 4351100cfcSAjay Bhargav #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 4451100cfcSAjay Bhargav #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 4551100cfcSAjay Bhargav #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 4651100cfcSAjay Bhargav #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity 4751100cfcSAjay Bhargav setting */ 4851100cfcSAjay Bhargav #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ 4951100cfcSAjay Bhargav #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ 5051100cfcSAjay Bhargav #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ 5151100cfcSAjay Bhargav #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ 5251100cfcSAjay Bhargav 5351100cfcSAjay Bhargav #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ 5451100cfcSAjay Bhargav #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ 5551100cfcSAjay Bhargav #define SSCR1_TINTE (1 << 19) /* Receiver Time-out 5651100cfcSAjay Bhargav Interrupt enable */ 5751100cfcSAjay Bhargav 5851100cfcSAjay Bhargav #define SSCR0_DSS 0x0f /* Data Size Select (mask) */ 5951100cfcSAjay Bhargav #define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ 6051100cfcSAjay Bhargav #define SSCR0_FRF 0x30 /* FRame Format (mask) */ 6151100cfcSAjay Bhargav #define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial 6251100cfcSAjay Bhargav Peripheral Interface */ 6351100cfcSAjay Bhargav #define SSCR0_TI (0x1 << 4) /* TI's Synchronous 6451100cfcSAjay Bhargav Serial Protocol (SSP) */ 6551100cfcSAjay Bhargav #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ 6651100cfcSAjay Bhargav #define SSCR0_ECS (1 << 6) /* External clock select */ 6751100cfcSAjay Bhargav #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port 6851100cfcSAjay Bhargav Enable */ 6951100cfcSAjay Bhargav 7051100cfcSAjay Bhargav #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ 7151100cfcSAjay Bhargav #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ 7251100cfcSAjay Bhargav #define SSSR_BSY (1 << 4) /* SSP Busy */ 7351100cfcSAjay Bhargav #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ 7451100cfcSAjay Bhargav #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ 7551100cfcSAjay Bhargav #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ 7651100cfcSAjay Bhargav #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 7751100cfcSAjay Bhargav 7851100cfcSAjay Bhargav #endif /* __ARMADA100_SPI_H_ */ 79