Home
last modified time | relevance | path

Searched refs:SSCR1_RIE (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h43 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ macro
/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */ macro
/openbmc/linux/drivers/input/mouse/
H A Dnavpoint.c57 | SSCR1_RIE /* RIE = 1; Receive FIFO interrupt enabled */
/openbmc/linux/drivers/spi/
H A Dspi-pxa2xx.c1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
/openbmc/qemu/hw/arm/
H A Dstrongarm.c1391 #define SSCR1_RIE (1 << 0) macro
1406 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); in strongarm_ssp_int_update()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h783 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ macro
/openbmc/u-boot/include/
H A DSA-1100.h1063 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ macro