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Searched refs:SRDS_PLLCR0_RFCK_SEL_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dcorenet_ds.c174 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/board/freescale/p2041rdb/
H A Dp2041rdb.c202 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/board/freescale/t1040qds/
H A Dt1040qds.c227 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/board/keymile/kmp204x/
H A Dkmp204x.c188 actual &= SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h324 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/openbmc/u-boot/board/freescale/t4qds/
H A Dt4240qds.c668 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c401 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); in p4080_erratum_serdes8()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h566 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds.c1180 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2543 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
2626 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro