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Searched refs:SRDS_PLLCR0_FRATE_SEL_5 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h333 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h575 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2553 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
2634 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro