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Searched refs:SPRN_L1CSR1 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S773 mtspr SPRN_L1CSR1,r2
775 mfspr r3,SPRN_L1CSR1
781 mtspr SPRN_L1CSR1,r3
784 mfspr r3,SPRN_L1CSR1
935 mtspr SPRN_L1CSR1,r3
938 mfspr r4,SPRN_L1CSR1
946 mtspr SPRN_L1CSR1,r3
949 mfspr r4,SPRN_L1CSR1
985 mfspr r11, SPRN_L1CSR1
989 mtspr SPRN_L1CSR1, r11
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H A Drelease.S104 mtspr SPRN_L1CSR1,r2
106 mfspr r3,SPRN_L1CSR1
112 mtspr SPRN_L1CSR1,r3
115 mfspr r3,SPRN_L1CSR1
/openbmc/linux/arch/powerpc/mm/nohash/
H A De500.c247 tmp = mfspr(SPRN_L1CSR1); in flush_instruction_cache()
249 mtspr(SPRN_L1CSR1, tmp); in flush_instruction_cache()
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_e500.S22 mfspr r0, SPRN_L1CSR1
27 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
H A Dtraps.c630 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); in machine_check_e500mc()
631 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) in machine_check_e500mc()
/openbmc/linux/arch/powerpc/kvm/
H A De500_emulate.c252 case SPRN_L1CSR1: in kvmppc_core_emulate_mtspr_e500()
381 case SPRN_L1CSR1: in kvmppc_core_emulate_mfspr_e500()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h491 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ macro
734 #define L1CSR1 SPRN_L1CSR1
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h174 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ macro