Home
last modified time | relevance | path

Searched refs:SIFIVE_U_DEV_DRAM (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Dsifive_u.c89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
155 (long)memmap[SIFIVE_U_DEV_DRAM].base); in create_fdt()
158 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, in create_fdt()
517 hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base; in sifive_u_machine_init()
538 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, in sifive_u_machine_init()
585 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; in sifive_u_machine_init()
607 fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, in sifive_u_machine_init()
608 memmap[SIFIVE_U_DEV_DRAM].size, in sifive_u_machine_init()
/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h95 SIFIVE_U_DEV_DRAM, enumerator