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Searched refs:SIFIVE_U_DEV_CLINT (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Dsifive_u.c71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
210 (long)memmap[SIFIVE_U_DEV_CLINT].base); in create_fdt()
215 0x0, memmap[SIFIVE_U_DEV_CLINT].base, in create_fdt()
216 0x0, memmap[SIFIVE_U_DEV_CLINT].size); in create_fdt()
846 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, in sifive_u_soc_realize()
848 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + in sifive_u_soc_realize()
/openbmc/qemu/include/hw/riscv/
H A Dsifive_u.h81 SIFIVE_U_DEV_CLINT, enumerator