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Searched refs:Rm (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \ argument
57 aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
212 #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \ argument
213 aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
216 #define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD) argument
217 #define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB) argument
218 #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS) argument
220 #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm) argument
222 #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm) argument
234 #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \ argument
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/openbmc/linux/arch/sh/math-emu/
H A Dmath.c52 #define Rm (regs->regs[m]) macro
160 MREAD(FRn, Rm + R0 + 4); in fmov_idx_reg()
162 MREAD(FRn, Rm + R0); in fmov_idx_reg()
164 MREAD(FRn, Rm + R0); in fmov_idx_reg()
176 MREAD(FRn, Rm + 4); in fmov_mem_reg()
178 MREAD(FRn, Rm); in fmov_mem_reg()
180 MREAD(FRn, Rm); in fmov_mem_reg()
192 MREAD(FRn, Rm + 4); in fmov_inc_reg()
194 MREAD(FRn, Rm); in fmov_inc_reg()
195 Rm += 8; in fmov_inc_reg()
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/openbmc/linux/arch/arm/mm/
H A Dabort-lv4t.S91 and r9, r8, #0x00f @ get Rm / low nibble of immediate value
95 ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
/openbmc/qemu/target/sh4/
H A Dtranslate.c708 TCGv Rm = REG(B7_4); in _decode_opc() local
714 tcg_gen_add_i32(result, Rm, Rn); in _decode_opc()
717 tcg_gen_xor_i32(t2, Rm, Rn); in _decode_opc()
936 TCGv Rm = REG(B7_4); in _decode_opc() local
942 tcg_gen_sub_i32(result, Rn, Rm); in _decode_opc()
945 tcg_gen_xor_i32(t2, Rn, Rm); in _decode_opc()
/openbmc/linux/arch/arm64/lib/
H A Dinsn.c1443 enum aarch64_insn_register Rm, in aarch64_insn_gen_extr() argument
1471 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm); in aarch64_insn_gen_extr()
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h651 enum aarch64_insn_register Rm,
/openbmc/qemu/target/arm/tcg/
H A Dt32.decode87 # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
H A Dmve.decode402 # VIDUP, VDDUP registers: Rm bits [3:1] from insn, bit 0 is 1;
/openbmc/openbmc/meta-raspberrypi/recipes-graphics/userland/files/
H A D0003-wayland-Add-Wayland-example.patch80 …˒�ʏ�Ǐ�ƣ����������z��s��{��w��g��<Xh=Yj;Uf8Rc2L^7NU4IQ+<D8COAO[;JWx��������Rm|l��F]mYn}7JW9KV=QX>N…
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc1596 * Rm (the second address op) must not overlap Rt or Rt + 1.