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Searched refs:R_SR (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/char/
H A Dcadence_uart.c116 #define R_SR (0x2C/4) macro
127 s->r[R_SR] = 0; in uart_update_status()
129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL in uart_update_status()
131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; in uart_update_status()
132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; in uart_update_status()
134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL in uart_update_status()
136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; in uart_update_status()
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()