Home
last modified time | relevance | path

Searched refs:R_IMR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/char/
H A Dcadence_uart.c109 #define R_IMR (0x10/4) macro
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
432 s->r[R_IMR] |= value; in uart_write()
435 s->r[R_IMR] &= ~value; in uart_write()
437 case R_IMR: /* imr (read only) */ in uart_write()
520 s->r[R_IMR] = 0; in cadence_uart_reset_init()
/openbmc/qemu/hw/misc/
H A Dxlnx-zynqmp-apu-ctrl.c73 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; in imr_update_irq()
88 s->regs[R_IMR] &= ~val; in ien_prew()
98 s->regs[R_IMR] |= val; in ids_prew()
H A Dxlnx-versal-pmc-iou-slcr.c805 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; in imr_update_irq()
820 s->regs[R_IMR] &= ~val; in ier_prew()
830 s->regs[R_IMR] |= val; in idr_prew()
/openbmc/qemu/hw/net/
H A Dcadence_gem.c579 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); in gem_set_isr()
604 s->regs_ro[R_IMR] = 0xFFFFFFFF; in gem_init_register_masks()
1459 s->regs[R_IMR] = 0x07ffffff; in gem_reset()
1655 s->regs[R_IMR] &= ~val; in gem_write()
1666 s->regs[R_IMR] |= val; in gem_write()