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Searched refs:RVU (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst4 Marvell OcteonTx2 RVU Kernel Drivers
21 Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC maps HW
25 RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual
27 and has privileges to provision RVU functional block's LFs to each of the
30 RVU managed networking functional blocks
37 RVU managed non-networking functional blocks
47 RVU functional blocks are highly configurable as per software requirements.
50 - Enables required number of RVU PFs based on number of physical links.
60 of RVU. Wrt networking there will be 3 flavours of drivers.
65 As mentioned above RVU PF0 is called the admin function (AF), this driver
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/
H A DKconfig3 # Marvell RVU Network drivers configuration
10 tristate "Marvell OcteonTX2 RVU Admin Function driver"
18 Unit's admin function manager which manages all RVU HW resources
20 enabled for other RVU device drivers to work.
/openbmc/qemu/target/riscv/
H A Dcpu.c45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
480 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
498 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
515 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); in rv64_thead_c906_cpu_init()
547 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
642 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
660 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
677 riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
699 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
1407 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
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H A Dcsr.c365 if (riscv_has_ext(env, RVU)) { in umode()
879 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH : 0; in write_mcyclecfg()
882 riscv_has_ext(env, RVU)) ? MCYCLECFG_BIT_VUINH : 0; in write_mcyclecfg()
905 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0; in write_mcyclecfgh()
908 riscv_has_ext(env, RVU)) ? MCYCLECFGH_BIT_VUINH : 0; in write_mcyclecfgh()
932 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFG_BIT_UINH : 0; in write_minstretcfg()
935 riscv_has_ext(env, RVU)) ? MINSTRETCFG_BIT_VUINH : 0; in write_minstretcfg()
956 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFGH_BIT_UINH : 0; in write_minstretcfgh()
959 riscv_has_ext(env, RVU)) ? MINSTRETCFGH_BIT_VUINH : 0; in write_minstretcfgh()
990 inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0; in write_mhpmevent()
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H A Dop_helper.c349 riscv_has_ext(env, RVU) ? PRV_U : PRV_M); in helper_mret()
H A Dcpu.h72 #define RVU RV('U') macro
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c440 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { in riscv_cpu_validate_set_extensions()
1087 MISA_CFG(RVU, true),
/openbmc/linux/
H A DMAINTAINERS12795 MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER