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Searched refs:RVI (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/comedi/drivers/tests/
H A Dni_routes_test.c26 #define RVI(table, src, dest) ((table)[(dest) * NI_NUM_NAMES + (src)]) macro
245 unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(17) && in test_ni_assign_device_routes()
246 RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == 0 && in test_ni_assign_device_routes()
247 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == 0 && in test_ni_assign_device_routes()
248 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(NI_PFI_OUTPUT_AI_CONVERT), in test_ni_assign_device_routes()
262 unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(20) && in test_ni_assign_device_routes()
263 RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == V(12) && in test_ni_assign_device_routes()
264 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == V(3) && in test_ni_assign_device_routes()
265 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(3), in test_ni_assign_device_routes()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c344 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; in riscv_cpu_validate_g()
428 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
434 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
446 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
1083 MISA_CFG(RVI, true),
1181 if (bit == RVI && !profile->enabled) { in cpu_set_profile()
/openbmc/qemu/target/riscv/
H A Dcpu.c44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
480 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
498 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
609 riscv_cpu_set_misa_ext(env, RVI); in rv64i_bare_cpu_init()
642 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
660 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
677 riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
699 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
714 riscv_cpu_set_misa_ext(env, RVI); in rv32i_bare_cpu_init()
1403 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
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H A Dxthead.decode50 # the regular RVI `add` instruction.
H A Dcpu.h63 #define RVI RV('I') macro
H A Dcsr.c1734 if (!(val & RVI && val & RVM && val & RVA && in write_misa()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I),
/openbmc/qemu/linux-user/
H A Dsyscall.c9004 value = riscv_has_ext(env, RVI) && in risc_hwprobe_fill_pairs()