/openbmc/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 344 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; in riscv_cpu_validate_g() 457 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions() 472 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 477 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 482 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 487 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 510 if (!riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 546 if (riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions() 563 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions() 864 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in cpu_enable_zc_implied_rules() [all …]
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzfa.c.inc | 35 REQUIRE_EXT(ctx, RVF); 184 REQUIRE_EXT(ctx, RVF); 201 REQUIRE_EXT(ctx, RVF); 286 REQUIRE_EXT(ctx, RVF); 303 REQUIRE_EXT(ctx, RVF); 437 REQUIRE_EXT(ctx, RVF); 452 REQUIRE_EXT(ctx, RVF);
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H A D | trans_rvf.c.inc | 30 REQUIRE_EXT(ctx, RVF); \ 36 if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \ 49 REQUIRE_EXT(ctx, RVF); 71 REQUIRE_EXT(ctx, RVF);
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H A D | trans_xthead.c.inc | 389 REQUIRE_EXT(ctx, RVF); 405 REQUIRE_EXT(ctx, RVF); 421 REQUIRE_EXT(ctx, RVF); 437 REQUIRE_EXT(ctx, RVF);
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H A D | trans_rvv.c.inc | 2191 * As RVF-only cpus always have values NaN-boxed to 64-bits, 2192 * RVF and RVD can be treated equally.
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/openbmc/qemu/target/riscv/ |
H A D | cpu.c | 44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, 480 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init() 642 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init() 699 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init() 1402 MISA_EXT_INFO(RVF, "f", "Single-precision float point"), 2216 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, 2279 .implied_misa_exts = RVF, 2285 .ext = RVF, 2344 .implied_misa_exts = RVF, 2381 .implied_misa_exts = RVF, [all …]
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H A D | gdbstub.c | 120 if (env->misa_ext & RVF) { in riscv_gdb_get_fpu() 336 } else if (env->misa_ext & RVF) { in riscv_cpu_register_gdb_regs_for_features()
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H A D | csr.c | 669 if (riscv_has_ext(env, RVF)) { in write_fflags() 688 if (riscv_has_ext(env, RVF)) { in write_frm() 708 if (riscv_has_ext(env, RVF)) { in write_fcsr() 1618 if (riscv_has_ext(env, RVF)) { in write_mstatus() 1735 val & RVF && val & RVD)) { in write_misa() 1757 if (!(env->misa_ext & RVF)) { in write_misa() 2565 if (!riscv_has_ext(env, RVF)) { in write_mstateen0() 2649 if (!riscv_has_ext(env, RVF)) { in write_hstateen0() 2739 if (!riscv_has_ext(env, RVF)) { in write_sstateen0()
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H A D | cpu.h | 67 #define RVF RV('F') macro
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H A D | cpu_helper.c | 199 if (!riscv_has_ext(env, RVF)) { in cpu_get_tb_cpu_state() 615 if (riscv_has_ext(env, RVF)) { in riscv_cpu_swap_hypervisor_regs()
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H A D | translate.c | 633 if (!has_ext(ctx, RVF)) { in mark_fs_dirty()
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/openbmc/qemu/target/riscv/kvm/ |
H A D | kvm-cpu.c | 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 660 if (riscv_has_ext(env, RVF)) { in kvm_riscv_get_regs_fp() 693 if (riscv_has_ext(env, RVF)) { in kvm_riscv_put_regs_fp()
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/openbmc/qemu/linux-user/ |
H A D | syscall.c | 9011 value = riscv_has_ext(env, RVF) && in risc_hwprobe_fill_pairs()
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