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Searched refs:RVE (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/linux-user/riscv/
H A Dcpu_loop.c107 if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { in target_cpu_copy_regs()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c428 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
434 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
1084 MISA_CFG(RVE, false),
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzce.c.inc120 if (has_ext(ctx, RVE) && rlist > 6) {
/openbmc/qemu/target/riscv/
H A Dcpu.c44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
615 riscv_cpu_set_misa_ext(env, RVE); in rv64e_bare_cpu_init()
720 riscv_cpu_set_misa_ext(env, RVE); in rv32e_bare_cpu_init()
1404 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
H A Dcpu.h64 #define RVE RV('E') /* E and I are mutually exclusive */ macro