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Searched refs:RST_BUS_OHCI0 (Results 1 – 25 of 37) sorted by relevance

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/openbmc/u-boot/include/dt-bindings/reset/
H A Dsun8i-v3s-ccu.h64 #define RST_BUS_OHCI0 22 macro
H A Dsun8i-a83t-ccu.h68 #define RST_BUS_OHCI0 20 macro
H A Dsun50i-a64-ccu.h67 #define RST_BUS_OHCI0 21 macro
H A Dsun8i-h3-ccu.h70 #define RST_BUS_OHCI0 22 macro
H A Dsun50i-h6-ccu.h57 #define RST_BUS_OHCI0 48 macro
H A Dsun8i-r40-ccu.h74 #define RST_BUS_OHCI0 26 macro
/openbmc/linux/include/dt-bindings/reset/
H A Dsun8i-v3s-ccu.h64 #define RST_BUS_OHCI0 22 macro
H A Dsun8i-a83t-ccu.h68 #define RST_BUS_OHCI0 20 macro
H A Dsun50i-a64-ccu.h67 #define RST_BUS_OHCI0 21 macro
H A Dsun8i-h3-ccu.h70 #define RST_BUS_OHCI0 22 macro
H A Dsun50i-h616-ccu.h51 #define RST_BUS_OHCI0 42 macro
H A Dsun50i-a100-ccu.h53 #define RST_BUS_OHCI0 44 macro
H A Dsun50i-h6-ccu.h57 #define RST_BUS_OHCI0 48 macro
H A Dsun20i-d1-ccu.h52 #define RST_BUS_OHCI0 42 macro
H A Dsun8i-r40-ccu.h74 #define RST_BUS_OHCI0 26 macro
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_a64.c59 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
H A Dclk_a83t.c57 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
H A Dclk_h3.c69 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
H A Dclk_r40.c74 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-v3s.c663 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
698 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
H A Dccu-sun8i-h3.c904 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
967 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi563 resets = <&ccu RST_BUS_OHCI0>,
577 resets = <&ccu RST_BUS_OHCI0>;
/openbmc/u-boot/arch/arm/dts/
H A Dsunxi-h3-h5.dtsi292 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
302 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
H A Dsun50i-a64.dtsi450 resets = <&ccu RST_BUS_OHCI0>,
461 resets = <&ccu RST_BUS_OHCI0>;
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi573 resets = <&ccu RST_BUS_OHCI0>,
587 resets = <&ccu RST_BUS_OHCI0>;

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