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Searched refs:RREG32_PLL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
51 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; in radeon_legacy_get_engine_clock()
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
81 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; in radeon_legacy_get_memory_clock()
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
122 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_read_clocks_OF()
152 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & in radeon_read_clocks_OF()
200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info()
216 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & in radeon_get_clock_info()
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H A Dradeon_legacy_crtc.c224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_wait_for_read_update_complete()
232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_write_update()
251 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); in radeon_pll2_wait_for_read_update_complete()
259 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); in radeon_pll2_write_update()
854 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & in radeon_set_pll()
903 RREG32_PLL(RADEON_P2PLL_CNTL)); in radeon_set_pll()
922 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_set_pll()
934 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && in radeon_set_pll()
935 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & in radeon_set_pll()
1009 RREG32_PLL(RADEON_PPLL_CNTL)); in radeon_set_pll()
H A Drs600.c260 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); in rs600_pm_misc()
277 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); in rs600_pm_misc()
289 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); in rs600_pm_misc()
297 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); in rs600_pm_misc()
304 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); in rs600_pm_misc()
H A Dradeon_combios.c1147 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); in radeon_legacy_get_lvds_info_from_regs()
1152 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_legacy_get_lvds_info_from_regs()
2990 val = RREG32_PLL(reg); in radeon_combios_external_tmds_setup()
3069 (RREG32_PLL in combios_parse_mmio_table()
3119 tmp = RREG32_PLL(addr); in combios_parse_pll_table()
3137 (RREG32_PLL in combios_parse_pll_table()
3145 if (RREG32_PLL in combios_parse_pll_table()
3153 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in combios_parse_pll_table()
3157 RREG32_PLL in combios_parse_pll_table()
H A Drv515.c480 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); in rv515_clock_startup()
482 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); in rv515_clock_startup()
484 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); in rv515_clock_startup()
H A Dr420.c199 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); in r420_clock_resume()
H A Dradeon_legacy_encoders.c120 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_lvds_update()
653 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()
1576 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_tv_dac_detect()
H A Dr100.c390 sclk_cntl = RREG32_PLL(SCLK_CNTL); in r100_pm_misc()
391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); in r100_pm_misc()
393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); in r100_pm_misc()
2717 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in r100_set_common_regs()
3891 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r100_clock_startup()
H A Dradeon_legacy_tv.c285 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
H A Dr300.c1363 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r300_clock_startup()
H A Dradeon.h2516 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) macro
2549 uint32_t tmp_ = RREG32_PLL(reg); \
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h1208 uint32_t tmp_ = RREG32_PLL(reg); \