1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc.
3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc.
4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse.
5771fe6b9SJerome Glisse *
6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse *
13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse *
16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse *
24771fe6b9SJerome Glisse * Authors: Dave Airlie
25771fe6b9SJerome Glisse * Alex Deucher
26771fe6b9SJerome Glisse * Jerome Glisse
27771fe6b9SJerome Glisse */
28c182615fSSam Ravnborg
2970967ab9SBen Hutchings #include <linux/firmware.h>
30e0cd3608SPaul Gortmaker #include <linux/module.h>
312ef79416SThomas Zimmermann #include <linux/pci.h>
322ef79416SThomas Zimmermann #include <linux/seq_file.h>
332ef79416SThomas Zimmermann #include <linux/slab.h>
3470967ab9SBen Hutchings
35c182615fSSam Ravnborg #include <drm/drm_device.h>
36c182615fSSam Ravnborg #include <drm/drm_file.h>
37c182615fSSam Ravnborg #include <drm/drm_fourcc.h>
38720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
39c182615fSSam Ravnborg #include <drm/drm_vblank.h>
40c182615fSSam Ravnborg #include <drm/radeon_drm.h>
41c182615fSSam Ravnborg
42c182615fSSam Ravnborg #include "atom.h"
43551ebd83SDave Airlie #include "r100_reg_safe.h"
44c182615fSSam Ravnborg #include "r100d.h"
45c182615fSSam Ravnborg #include "radeon.h"
46c182615fSSam Ravnborg #include "radeon_asic.h"
47c182615fSSam Ravnborg #include "radeon_reg.h"
48551ebd83SDave Airlie #include "rn50_reg_safe.h"
49c182615fSSam Ravnborg #include "rs100d.h"
50c182615fSSam Ravnborg #include "rv200d.h"
51c182615fSSam Ravnborg #include "rv250d.h"
52551ebd83SDave Airlie
5370967ab9SBen Hutchings /* Firmware Names */
5470967ab9SBen Hutchings #define FIRMWARE_R100 "radeon/R100_cp.bin"
5570967ab9SBen Hutchings #define FIRMWARE_R200 "radeon/R200_cp.bin"
5670967ab9SBen Hutchings #define FIRMWARE_R300 "radeon/R300_cp.bin"
5770967ab9SBen Hutchings #define FIRMWARE_R420 "radeon/R420_cp.bin"
5870967ab9SBen Hutchings #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
5970967ab9SBen Hutchings #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
6070967ab9SBen Hutchings #define FIRMWARE_R520 "radeon/R520_cp.bin"
6170967ab9SBen Hutchings
6270967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R100);
6370967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R200);
6470967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R300);
6570967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R420);
6670967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS690);
6770967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS600);
6870967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R520);
69771fe6b9SJerome Glisse
70551ebd83SDave Airlie #include "r100_track.h"
71551ebd83SDave Airlie
7248ef779fSAlex Deucher /* This files gather functions specifics to:
7348ef779fSAlex Deucher * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
7448ef779fSAlex Deucher * and others in some cases.
7548ef779fSAlex Deucher */
7648ef779fSAlex Deucher
r100_is_in_vblank(struct radeon_device * rdev,int crtc)772b48b968SAlex Deucher static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
782b48b968SAlex Deucher {
792b48b968SAlex Deucher if (crtc == 0) {
802b48b968SAlex Deucher if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
812b48b968SAlex Deucher return true;
822b48b968SAlex Deucher else
832b48b968SAlex Deucher return false;
842b48b968SAlex Deucher } else {
852b48b968SAlex Deucher if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
862b48b968SAlex Deucher return true;
872b48b968SAlex Deucher else
882b48b968SAlex Deucher return false;
892b48b968SAlex Deucher }
902b48b968SAlex Deucher }
912b48b968SAlex Deucher
r100_is_counter_moving(struct radeon_device * rdev,int crtc)922b48b968SAlex Deucher static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
932b48b968SAlex Deucher {
942b48b968SAlex Deucher u32 vline1, vline2;
952b48b968SAlex Deucher
962b48b968SAlex Deucher if (crtc == 0) {
972b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
982b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
992b48b968SAlex Deucher } else {
1002b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1012b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1022b48b968SAlex Deucher }
1032b48b968SAlex Deucher if (vline1 != vline2)
1042b48b968SAlex Deucher return true;
1052b48b968SAlex Deucher else
1062b48b968SAlex Deucher return false;
1072b48b968SAlex Deucher }
1082b48b968SAlex Deucher
10948ef779fSAlex Deucher /**
11048ef779fSAlex Deucher * r100_wait_for_vblank - vblank wait asic callback.
11148ef779fSAlex Deucher *
11248ef779fSAlex Deucher * @rdev: radeon_device pointer
11348ef779fSAlex Deucher * @crtc: crtc to wait for vblank on
11448ef779fSAlex Deucher *
11548ef779fSAlex Deucher * Wait for vblank on the requested crtc (r1xx-r4xx).
11648ef779fSAlex Deucher */
r100_wait_for_vblank(struct radeon_device * rdev,int crtc)1173ae19b75SAlex Deucher void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
1183ae19b75SAlex Deucher {
1192b48b968SAlex Deucher unsigned i = 0;
1203ae19b75SAlex Deucher
12194f768fdSAlex Deucher if (crtc >= rdev->num_crtc)
12294f768fdSAlex Deucher return;
12394f768fdSAlex Deucher
12494f768fdSAlex Deucher if (crtc == 0) {
1252b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
1262b48b968SAlex Deucher return;
1273ae19b75SAlex Deucher } else {
1282b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
1292b48b968SAlex Deucher return;
1303ae19b75SAlex Deucher }
1312b48b968SAlex Deucher
1322b48b968SAlex Deucher /* depending on when we hit vblank, we may be close to active; if so,
1332b48b968SAlex Deucher * wait for another frame.
1342b48b968SAlex Deucher */
1352b48b968SAlex Deucher while (r100_is_in_vblank(rdev, crtc)) {
1362b48b968SAlex Deucher if (i++ % 100 == 0) {
1372b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc))
1383ae19b75SAlex Deucher break;
1393ae19b75SAlex Deucher }
1403ae19b75SAlex Deucher }
1412b48b968SAlex Deucher
1422b48b968SAlex Deucher while (!r100_is_in_vblank(rdev, crtc)) {
1432b48b968SAlex Deucher if (i++ % 100 == 0) {
1442b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc))
1452b48b968SAlex Deucher break;
1462b48b968SAlex Deucher }
1473ae19b75SAlex Deucher }
1483ae19b75SAlex Deucher }
1493ae19b75SAlex Deucher
15048ef779fSAlex Deucher /**
15148ef779fSAlex Deucher * r100_page_flip - pageflip callback.
15248ef779fSAlex Deucher *
15348ef779fSAlex Deucher * @rdev: radeon_device pointer
15448ef779fSAlex Deucher * @crtc_id: crtc to cleanup pageflip on
15548ef779fSAlex Deucher * @crtc_base: new address of the crtc (GPU MC address)
1560d8357c2SLee Jones * @async: asynchronous flip
15748ef779fSAlex Deucher *
15848ef779fSAlex Deucher * Does the actual pageflip (r1xx-r4xx).
15948ef779fSAlex Deucher * During vblank we take the crtc lock and wait for the update_pending
16048ef779fSAlex Deucher * bit to go high, when it does, we release the lock, and allow the
16148ef779fSAlex Deucher * double buffered update to take place.
16248ef779fSAlex Deucher */
r100_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base,bool async)163c63dd758SMichel Dänzer void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
1646f34be50SAlex Deucher {
1656f34be50SAlex Deucher struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
166c841e552SZhenneng Li uint32_t crtc_pitch, pitch_pixels;
167c841e552SZhenneng Li struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
1686f34be50SAlex Deucher u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
169f6496479SAlex Deucher int i;
1706f34be50SAlex Deucher
1716f34be50SAlex Deucher /* Lock the graphics update lock */
1726f34be50SAlex Deucher /* update the scanout addresses */
1736f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
1746f34be50SAlex Deucher
175c841e552SZhenneng Li /* update pitch */
176c841e552SZhenneng Li pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
177c841e552SZhenneng Li crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,
178c841e552SZhenneng Li fb->format->cpp[0] * 8 * 8);
179c841e552SZhenneng Li crtc_pitch |= crtc_pitch << 16;
180c841e552SZhenneng Li WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
181c841e552SZhenneng Li
182acb32506SAlex Deucher /* Wait for update_pending to go high. */
183f6496479SAlex Deucher for (i = 0; i < rdev->usec_timeout; i++) {
184f6496479SAlex Deucher if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
185f6496479SAlex Deucher break;
186f6496479SAlex Deucher udelay(1);
187f6496479SAlex Deucher }
188acb32506SAlex Deucher DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
1896f34be50SAlex Deucher
1906f34be50SAlex Deucher /* Unlock the lock, so double-buffering can take place inside vblank */
1916f34be50SAlex Deucher tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
1926f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
1936f34be50SAlex Deucher
194157fa14dSChristian König }
195157fa14dSChristian König
196157fa14dSChristian König /**
197157fa14dSChristian König * r100_page_flip_pending - check if page flip is still pending
198157fa14dSChristian König *
199157fa14dSChristian König * @rdev: radeon_device pointer
200157fa14dSChristian König * @crtc_id: crtc to check
201157fa14dSChristian König *
202157fa14dSChristian König * Check if the last pagefilp is still pending (r1xx-r4xx).
203157fa14dSChristian König * Returns the current update pending status.
204157fa14dSChristian König */
r100_page_flip_pending(struct radeon_device * rdev,int crtc_id)205157fa14dSChristian König bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
206157fa14dSChristian König {
207157fa14dSChristian König struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
208157fa14dSChristian König
2096f34be50SAlex Deucher /* Return current update_pending status: */
210157fa14dSChristian König return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
211157fa14dSChristian König RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
2126f34be50SAlex Deucher }
2136f34be50SAlex Deucher
21448ef779fSAlex Deucher /**
21548ef779fSAlex Deucher * r100_pm_get_dynpm_state - look up dynpm power state callback.
21648ef779fSAlex Deucher *
21748ef779fSAlex Deucher * @rdev: radeon_device pointer
21848ef779fSAlex Deucher *
21948ef779fSAlex Deucher * Look up the optimal power state based on the
22048ef779fSAlex Deucher * current state of the GPU (r1xx-r5xx).
22148ef779fSAlex Deucher * Used for dynpm only.
22248ef779fSAlex Deucher */
r100_pm_get_dynpm_state(struct radeon_device * rdev)223ce8f5370SAlex Deucher void r100_pm_get_dynpm_state(struct radeon_device *rdev)
224a48b9b4eSAlex Deucher {
225a48b9b4eSAlex Deucher int i;
226ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = true;
227ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = true;
228a48b9b4eSAlex Deucher
229ce8f5370SAlex Deucher switch (rdev->pm.dynpm_planned_action) {
230ce8f5370SAlex Deucher case DYNPM_ACTION_MINIMUM:
231a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 0;
232ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false;
233a48b9b4eSAlex Deucher break;
234ce8f5370SAlex Deucher case DYNPM_ACTION_DOWNCLOCK:
235a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == 0) {
236a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false;
238a48b9b4eSAlex Deucher } else {
239a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) {
240a48b9b4eSAlex Deucher for (i = 0; i < rdev->pm.num_power_states; i++) {
241d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
242a48b9b4eSAlex Deucher continue;
243a48b9b4eSAlex Deucher else if (i >= rdev->pm.current_power_state_index) {
244a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
245a48b9b4eSAlex Deucher break;
246a48b9b4eSAlex Deucher } else {
247a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i;
248a48b9b4eSAlex Deucher break;
249a48b9b4eSAlex Deucher }
250a48b9b4eSAlex Deucher }
251a48b9b4eSAlex Deucher } else
252a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index =
253a48b9b4eSAlex Deucher rdev->pm.current_power_state_index - 1;
254a48b9b4eSAlex Deucher }
255d7311171SAlex Deucher /* don't use the power state if crtcs are active and no display flag is set */
256d7311171SAlex Deucher if ((rdev->pm.active_crtc_count > 0) &&
257d7311171SAlex Deucher (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
258d7311171SAlex Deucher RADEON_PM_MODE_NO_DISPLAY)) {
259d7311171SAlex Deucher rdev->pm.requested_power_state_index++;
260d7311171SAlex Deucher }
261a48b9b4eSAlex Deucher break;
262ce8f5370SAlex Deucher case DYNPM_ACTION_UPCLOCK:
263a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
264a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
265ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false;
266a48b9b4eSAlex Deucher } else {
267a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) {
268a48b9b4eSAlex Deucher for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
269d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
270a48b9b4eSAlex Deucher continue;
271a48b9b4eSAlex Deucher else if (i <= rdev->pm.current_power_state_index) {
272a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
273a48b9b4eSAlex Deucher break;
274a48b9b4eSAlex Deucher } else {
275a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i;
276a48b9b4eSAlex Deucher break;
277a48b9b4eSAlex Deucher }
278a48b9b4eSAlex Deucher }
279a48b9b4eSAlex Deucher } else
280a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index =
281a48b9b4eSAlex Deucher rdev->pm.current_power_state_index + 1;
282a48b9b4eSAlex Deucher }
283a48b9b4eSAlex Deucher break;
284ce8f5370SAlex Deucher case DYNPM_ACTION_DEFAULT:
28558e21dffSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
286ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false;
28758e21dffSAlex Deucher break;
288ce8f5370SAlex Deucher case DYNPM_ACTION_NONE:
289a48b9b4eSAlex Deucher default:
290a48b9b4eSAlex Deucher DRM_ERROR("Requested mode for not defined action\n");
291a48b9b4eSAlex Deucher return;
292a48b9b4eSAlex Deucher }
293a48b9b4eSAlex Deucher /* only one clock mode per power state */
294a48b9b4eSAlex Deucher rdev->pm.requested_clock_mode_index = 0;
295a48b9b4eSAlex Deucher
296d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
297a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index].
298a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].sclk,
299a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index].
300a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].mclk,
301a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index].
30279daedc9SAlex Deucher pcie_lanes);
303a48b9b4eSAlex Deucher }
304a48b9b4eSAlex Deucher
30548ef779fSAlex Deucher /**
30648ef779fSAlex Deucher * r100_pm_init_profile - Initialize power profiles callback.
30748ef779fSAlex Deucher *
30848ef779fSAlex Deucher * @rdev: radeon_device pointer
30948ef779fSAlex Deucher *
31048ef779fSAlex Deucher * Initialize the power states used in profile mode
31148ef779fSAlex Deucher * (r1xx-r3xx).
31248ef779fSAlex Deucher * Used for profile mode only.
31348ef779fSAlex Deucher */
r100_pm_init_profile(struct radeon_device * rdev)314ce8f5370SAlex Deucher void r100_pm_init_profile(struct radeon_device *rdev)
315bae6b562SAlex Deucher {
316ce8f5370SAlex Deucher /* default */
317ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321ce8f5370SAlex Deucher /* low sh */
322ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
326c9e75b21SAlex Deucher /* mid sh */
327c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
331ce8f5370SAlex Deucher /* high sh */
332ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336ce8f5370SAlex Deucher /* low mh */
337ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
341c9e75b21SAlex Deucher /* mid mh */
342c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
346ce8f5370SAlex Deucher /* high mh */
347ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
349ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
351bae6b562SAlex Deucher }
352bae6b562SAlex Deucher
35348ef779fSAlex Deucher /**
35448ef779fSAlex Deucher * r100_pm_misc - set additional pm hw parameters callback.
35548ef779fSAlex Deucher *
35648ef779fSAlex Deucher * @rdev: radeon_device pointer
35748ef779fSAlex Deucher *
35848ef779fSAlex Deucher * Set non-clock parameters associated with a power state
35948ef779fSAlex Deucher * (voltage, pcie lanes, etc.) (r1xx-r4xx).
36048ef779fSAlex Deucher */
r100_pm_misc(struct radeon_device * rdev)36149e02b73SAlex Deucher void r100_pm_misc(struct radeon_device *rdev)
36249e02b73SAlex Deucher {
36349e02b73SAlex Deucher int requested_index = rdev->pm.requested_power_state_index;
36449e02b73SAlex Deucher struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
36549e02b73SAlex Deucher struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
36649e02b73SAlex Deucher u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
36749e02b73SAlex Deucher
36849e02b73SAlex Deucher if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
36949e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
37049e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg);
37149e02b73SAlex Deucher if (voltage->active_high)
37249e02b73SAlex Deucher tmp |= voltage->gpio.mask;
37349e02b73SAlex Deucher else
37449e02b73SAlex Deucher tmp &= ~(voltage->gpio.mask);
37549e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp);
37649e02b73SAlex Deucher if (voltage->delay)
37749e02b73SAlex Deucher udelay(voltage->delay);
37849e02b73SAlex Deucher } else {
37949e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg);
38049e02b73SAlex Deucher if (voltage->active_high)
38149e02b73SAlex Deucher tmp &= ~voltage->gpio.mask;
38249e02b73SAlex Deucher else
38349e02b73SAlex Deucher tmp |= voltage->gpio.mask;
38449e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp);
38549e02b73SAlex Deucher if (voltage->delay)
38649e02b73SAlex Deucher udelay(voltage->delay);
38749e02b73SAlex Deucher }
38849e02b73SAlex Deucher }
38949e02b73SAlex Deucher
39049e02b73SAlex Deucher sclk_cntl = RREG32_PLL(SCLK_CNTL);
39149e02b73SAlex Deucher sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
39249e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
39349e02b73SAlex Deucher sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
39449e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
39549e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
39649e02b73SAlex Deucher sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
39749e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
39849e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
39949e02b73SAlex Deucher else
40049e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
40149e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
40249e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
40349e02b73SAlex Deucher else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
40449e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
40549e02b73SAlex Deucher } else
40649e02b73SAlex Deucher sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
40749e02b73SAlex Deucher
40849e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
40949e02b73SAlex Deucher sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
41049e02b73SAlex Deucher if (voltage->delay) {
41149e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DROP_SYNC;
41249e02b73SAlex Deucher switch (voltage->delay) {
41349e02b73SAlex Deucher case 33:
41449e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
41549e02b73SAlex Deucher break;
41649e02b73SAlex Deucher case 66:
41749e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
41849e02b73SAlex Deucher break;
41949e02b73SAlex Deucher case 99:
42049e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
42149e02b73SAlex Deucher break;
42249e02b73SAlex Deucher case 132:
42349e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
42449e02b73SAlex Deucher break;
42549e02b73SAlex Deucher }
42649e02b73SAlex Deucher } else
42749e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
42849e02b73SAlex Deucher } else
42949e02b73SAlex Deucher sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
43049e02b73SAlex Deucher
43149e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
43249e02b73SAlex Deucher sclk_cntl &= ~FORCE_HDP;
43349e02b73SAlex Deucher else
43449e02b73SAlex Deucher sclk_cntl |= FORCE_HDP;
43549e02b73SAlex Deucher
43649e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL, sclk_cntl);
43749e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
43849e02b73SAlex Deucher WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
43949e02b73SAlex Deucher
44049e02b73SAlex Deucher /* set pcie lanes */
44149e02b73SAlex Deucher if ((rdev->flags & RADEON_IS_PCIE) &&
44249e02b73SAlex Deucher !(rdev->flags & RADEON_IS_IGP) &&
443798bcf73SAlex Deucher rdev->asic->pm.set_pcie_lanes &&
44449e02b73SAlex Deucher (ps->pcie_lanes !=
44549e02b73SAlex Deucher rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
44649e02b73SAlex Deucher radeon_set_pcie_lanes(rdev,
44749e02b73SAlex Deucher ps->pcie_lanes);
448d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
44949e02b73SAlex Deucher }
45049e02b73SAlex Deucher }
45149e02b73SAlex Deucher
45248ef779fSAlex Deucher /**
45348ef779fSAlex Deucher * r100_pm_prepare - pre-power state change callback.
45448ef779fSAlex Deucher *
45548ef779fSAlex Deucher * @rdev: radeon_device pointer
45648ef779fSAlex Deucher *
45748ef779fSAlex Deucher * Prepare for a power state change (r1xx-r4xx).
45848ef779fSAlex Deucher */
r100_pm_prepare(struct radeon_device * rdev)45949e02b73SAlex Deucher void r100_pm_prepare(struct radeon_device *rdev)
46049e02b73SAlex Deucher {
461*5e3a0f77SWu Hoi Pok struct drm_device *ddev = rdev_to_drm(rdev);
46249e02b73SAlex Deucher struct drm_crtc *crtc;
46349e02b73SAlex Deucher struct radeon_crtc *radeon_crtc;
46449e02b73SAlex Deucher u32 tmp;
46549e02b73SAlex Deucher
46649e02b73SAlex Deucher /* disable any active CRTCs */
46749e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
46849e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc);
46949e02b73SAlex Deucher if (radeon_crtc->enabled) {
47049e02b73SAlex Deucher if (radeon_crtc->crtc_id) {
47149e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
47249e02b73SAlex Deucher tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
47349e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
47449e02b73SAlex Deucher } else {
47549e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL);
47649e02b73SAlex Deucher tmp |= RADEON_CRTC_DISP_REQ_EN_B;
47749e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp);
47849e02b73SAlex Deucher }
47949e02b73SAlex Deucher }
48049e02b73SAlex Deucher }
48149e02b73SAlex Deucher }
48249e02b73SAlex Deucher
48348ef779fSAlex Deucher /**
48448ef779fSAlex Deucher * r100_pm_finish - post-power state change callback.
48548ef779fSAlex Deucher *
48648ef779fSAlex Deucher * @rdev: radeon_device pointer
48748ef779fSAlex Deucher *
48848ef779fSAlex Deucher * Clean up after a power state change (r1xx-r4xx).
48948ef779fSAlex Deucher */
r100_pm_finish(struct radeon_device * rdev)49049e02b73SAlex Deucher void r100_pm_finish(struct radeon_device *rdev)
49149e02b73SAlex Deucher {
492*5e3a0f77SWu Hoi Pok struct drm_device *ddev = rdev_to_drm(rdev);
49349e02b73SAlex Deucher struct drm_crtc *crtc;
49449e02b73SAlex Deucher struct radeon_crtc *radeon_crtc;
49549e02b73SAlex Deucher u32 tmp;
49649e02b73SAlex Deucher
49749e02b73SAlex Deucher /* enable any active CRTCs */
49849e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
49949e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc);
50049e02b73SAlex Deucher if (radeon_crtc->enabled) {
50149e02b73SAlex Deucher if (radeon_crtc->crtc_id) {
50249e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
50349e02b73SAlex Deucher tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
50449e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
50549e02b73SAlex Deucher } else {
50649e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL);
50749e02b73SAlex Deucher tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
50849e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp);
50949e02b73SAlex Deucher }
51049e02b73SAlex Deucher }
51149e02b73SAlex Deucher }
51249e02b73SAlex Deucher }
51349e02b73SAlex Deucher
51448ef779fSAlex Deucher /**
51548ef779fSAlex Deucher * r100_gui_idle - gui idle callback.
51648ef779fSAlex Deucher *
51748ef779fSAlex Deucher * @rdev: radeon_device pointer
51848ef779fSAlex Deucher *
51948ef779fSAlex Deucher * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
52048ef779fSAlex Deucher * Returns true if idle, false if not.
52148ef779fSAlex Deucher */
r100_gui_idle(struct radeon_device * rdev)522def9ba9cSAlex Deucher bool r100_gui_idle(struct radeon_device *rdev)
523def9ba9cSAlex Deucher {
524def9ba9cSAlex Deucher if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
525def9ba9cSAlex Deucher return false;
526def9ba9cSAlex Deucher else
527def9ba9cSAlex Deucher return true;
528def9ba9cSAlex Deucher }
529def9ba9cSAlex Deucher
53005a05c50SAlex Deucher /* hpd for digital panel detect/disconnect */
53148ef779fSAlex Deucher /**
53248ef779fSAlex Deucher * r100_hpd_sense - hpd sense callback.
53348ef779fSAlex Deucher *
53448ef779fSAlex Deucher * @rdev: radeon_device pointer
53548ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin
53648ef779fSAlex Deucher *
53748ef779fSAlex Deucher * Checks if a digital monitor is connected (r1xx-r4xx).
53848ef779fSAlex Deucher * Returns true if connected, false if not connected.
53948ef779fSAlex Deucher */
r100_hpd_sense(struct radeon_device * rdev,enum radeon_hpd_id hpd)54005a05c50SAlex Deucher bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
54105a05c50SAlex Deucher {
54205a05c50SAlex Deucher bool connected = false;
54305a05c50SAlex Deucher
54405a05c50SAlex Deucher switch (hpd) {
54505a05c50SAlex Deucher case RADEON_HPD_1:
54605a05c50SAlex Deucher if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
54705a05c50SAlex Deucher connected = true;
54805a05c50SAlex Deucher break;
54905a05c50SAlex Deucher case RADEON_HPD_2:
55005a05c50SAlex Deucher if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
55105a05c50SAlex Deucher connected = true;
55205a05c50SAlex Deucher break;
55305a05c50SAlex Deucher default:
55405a05c50SAlex Deucher break;
55505a05c50SAlex Deucher }
55605a05c50SAlex Deucher return connected;
55705a05c50SAlex Deucher }
55805a05c50SAlex Deucher
55948ef779fSAlex Deucher /**
56048ef779fSAlex Deucher * r100_hpd_set_polarity - hpd set polarity callback.
56148ef779fSAlex Deucher *
56248ef779fSAlex Deucher * @rdev: radeon_device pointer
56348ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin
56448ef779fSAlex Deucher *
56548ef779fSAlex Deucher * Set the polarity of the hpd pin (r1xx-r4xx).
56648ef779fSAlex Deucher */
r100_hpd_set_polarity(struct radeon_device * rdev,enum radeon_hpd_id hpd)56705a05c50SAlex Deucher void r100_hpd_set_polarity(struct radeon_device *rdev,
56805a05c50SAlex Deucher enum radeon_hpd_id hpd)
56905a05c50SAlex Deucher {
57005a05c50SAlex Deucher u32 tmp;
57105a05c50SAlex Deucher bool connected = r100_hpd_sense(rdev, hpd);
57205a05c50SAlex Deucher
57305a05c50SAlex Deucher switch (hpd) {
57405a05c50SAlex Deucher case RADEON_HPD_1:
57505a05c50SAlex Deucher tmp = RREG32(RADEON_FP_GEN_CNTL);
57605a05c50SAlex Deucher if (connected)
57705a05c50SAlex Deucher tmp &= ~RADEON_FP_DETECT_INT_POL;
57805a05c50SAlex Deucher else
57905a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_INT_POL;
58005a05c50SAlex Deucher WREG32(RADEON_FP_GEN_CNTL, tmp);
58105a05c50SAlex Deucher break;
58205a05c50SAlex Deucher case RADEON_HPD_2:
58305a05c50SAlex Deucher tmp = RREG32(RADEON_FP2_GEN_CNTL);
58405a05c50SAlex Deucher if (connected)
58505a05c50SAlex Deucher tmp &= ~RADEON_FP2_DETECT_INT_POL;
58605a05c50SAlex Deucher else
58705a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_INT_POL;
58805a05c50SAlex Deucher WREG32(RADEON_FP2_GEN_CNTL, tmp);
58905a05c50SAlex Deucher break;
59005a05c50SAlex Deucher default:
59105a05c50SAlex Deucher break;
59205a05c50SAlex Deucher }
59305a05c50SAlex Deucher }
59405a05c50SAlex Deucher
59548ef779fSAlex Deucher /**
59648ef779fSAlex Deucher * r100_hpd_init - hpd setup callback.
59748ef779fSAlex Deucher *
59848ef779fSAlex Deucher * @rdev: radeon_device pointer
59948ef779fSAlex Deucher *
60048ef779fSAlex Deucher * Setup the hpd pins used by the card (r1xx-r4xx).
60148ef779fSAlex Deucher * Set the polarity, and enable the hpd interrupts.
60248ef779fSAlex Deucher */
r100_hpd_init(struct radeon_device * rdev)60305a05c50SAlex Deucher void r100_hpd_init(struct radeon_device *rdev)
60405a05c50SAlex Deucher {
605*5e3a0f77SWu Hoi Pok struct drm_device *dev = rdev_to_drm(rdev);
60605a05c50SAlex Deucher struct drm_connector *connector;
607fb98257aSChristian Koenig unsigned enable = 0;
60805a05c50SAlex Deucher
60905a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
61005a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector);
611b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
612fb98257aSChristian Koenig enable |= 1 << radeon_connector->hpd.hpd;
61364912e99SAlex Deucher radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
61405a05c50SAlex Deucher }
615fb98257aSChristian Koenig radeon_irq_kms_enable_hpd(rdev, enable);
61605a05c50SAlex Deucher }
61705a05c50SAlex Deucher
61848ef779fSAlex Deucher /**
61948ef779fSAlex Deucher * r100_hpd_fini - hpd tear down callback.
62048ef779fSAlex Deucher *
62148ef779fSAlex Deucher * @rdev: radeon_device pointer
62248ef779fSAlex Deucher *
62348ef779fSAlex Deucher * Tear down the hpd pins used by the card (r1xx-r4xx).
62448ef779fSAlex Deucher * Disable the hpd interrupts.
62548ef779fSAlex Deucher */
r100_hpd_fini(struct radeon_device * rdev)62605a05c50SAlex Deucher void r100_hpd_fini(struct radeon_device *rdev)
62705a05c50SAlex Deucher {
628*5e3a0f77SWu Hoi Pok struct drm_device *dev = rdev_to_drm(rdev);
62905a05c50SAlex Deucher struct drm_connector *connector;
630fb98257aSChristian Koenig unsigned disable = 0;
63105a05c50SAlex Deucher
63205a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
63305a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector);
634b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
635fb98257aSChristian Koenig disable |= 1 << radeon_connector->hpd.hpd;
63605a05c50SAlex Deucher }
637fb98257aSChristian Koenig radeon_irq_kms_disable_hpd(rdev, disable);
63805a05c50SAlex Deucher }
63905a05c50SAlex Deucher
640771fe6b9SJerome Glisse /*
641771fe6b9SJerome Glisse * PCI GART
642771fe6b9SJerome Glisse */
r100_pci_gart_tlb_flush(struct radeon_device * rdev)643771fe6b9SJerome Glisse void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
644771fe6b9SJerome Glisse {
645771fe6b9SJerome Glisse /* TODO: can we do somethings here ? */
646771fe6b9SJerome Glisse /* It seems hw only cache one entry so we should discard this
647771fe6b9SJerome Glisse * entry otherwise if first GPU GART read hit this entry it
648771fe6b9SJerome Glisse * could end up in wrong address. */
649771fe6b9SJerome Glisse }
650771fe6b9SJerome Glisse
r100_pci_gart_init(struct radeon_device * rdev)6514aac0473SJerome Glisse int r100_pci_gart_init(struct radeon_device *rdev)
6524aac0473SJerome Glisse {
6534aac0473SJerome Glisse int r;
6544aac0473SJerome Glisse
655c9a1be96SJerome Glisse if (rdev->gart.ptr) {
656fce7d61bSJoe Perches WARN(1, "R100 PCI GART already initialized\n");
6574aac0473SJerome Glisse return 0;
6584aac0473SJerome Glisse }
6594aac0473SJerome Glisse /* Initialize common gart structure */
6604aac0473SJerome Glisse r = radeon_gart_init(rdev);
6614aac0473SJerome Glisse if (r)
6624aac0473SJerome Glisse return r;
6634aac0473SJerome Glisse rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
664c5b3b850SAlex Deucher rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
665cb658906SMichel Dänzer rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
666c5b3b850SAlex Deucher rdev->asic->gart.set_page = &r100_pci_gart_set_page;
6674aac0473SJerome Glisse return radeon_gart_table_ram_alloc(rdev);
6684aac0473SJerome Glisse }
6694aac0473SJerome Glisse
r100_pci_gart_enable(struct radeon_device * rdev)670771fe6b9SJerome Glisse int r100_pci_gart_enable(struct radeon_device *rdev)
671771fe6b9SJerome Glisse {
672771fe6b9SJerome Glisse uint32_t tmp;
673771fe6b9SJerome Glisse
674771fe6b9SJerome Glisse /* discard memory request outside of configured range */
675771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp);
677771fe6b9SJerome Glisse /* set address range for PCI address translate */
678d594e46aSJerome Glisse WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
679d594e46aSJerome Glisse WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
680771fe6b9SJerome Glisse /* set PCI GART page-table base address */
681771fe6b9SJerome Glisse WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
682771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
683771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp);
684771fe6b9SJerome Glisse r100_pci_gart_tlb_flush(rdev);
68543caf451SMichel Dänzer DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
686fcf4de5aSTormod Volden (unsigned)(rdev->mc.gtt_size >> 20),
687fcf4de5aSTormod Volden (unsigned long long)rdev->gart.table_addr);
688771fe6b9SJerome Glisse rdev->gart.ready = true;
689771fe6b9SJerome Glisse return 0;
690771fe6b9SJerome Glisse }
691771fe6b9SJerome Glisse
r100_pci_gart_disable(struct radeon_device * rdev)692771fe6b9SJerome Glisse void r100_pci_gart_disable(struct radeon_device *rdev)
693771fe6b9SJerome Glisse {
694771fe6b9SJerome Glisse uint32_t tmp;
695771fe6b9SJerome Glisse
696771fe6b9SJerome Glisse /* discard memory request outside of configured range */
697771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
698771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
699771fe6b9SJerome Glisse WREG32(RADEON_AIC_LO_ADDR, 0);
700771fe6b9SJerome Glisse WREG32(RADEON_AIC_HI_ADDR, 0);
701771fe6b9SJerome Glisse }
702771fe6b9SJerome Glisse
r100_pci_gart_get_page_entry(uint64_t addr,uint32_t flags)703cb658906SMichel Dänzer uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
704cb658906SMichel Dänzer {
705cb658906SMichel Dänzer return addr;
706cb658906SMichel Dänzer }
707cb658906SMichel Dänzer
r100_pci_gart_set_page(struct radeon_device * rdev,unsigned i,uint64_t entry)7087f90fc96SChristian König void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
709cb658906SMichel Dänzer uint64_t entry)
710771fe6b9SJerome Glisse {
711c9a1be96SJerome Glisse u32 *gtt = rdev->gart.ptr;
712cb658906SMichel Dänzer gtt[i] = cpu_to_le32(lower_32_bits(entry));
713771fe6b9SJerome Glisse }
714771fe6b9SJerome Glisse
r100_pci_gart_fini(struct radeon_device * rdev)7154aac0473SJerome Glisse void r100_pci_gart_fini(struct radeon_device *rdev)
716771fe6b9SJerome Glisse {
717f9274562SJerome Glisse radeon_gart_fini(rdev);
718771fe6b9SJerome Glisse r100_pci_gart_disable(rdev);
7194aac0473SJerome Glisse radeon_gart_table_ram_free(rdev);
720771fe6b9SJerome Glisse }
721771fe6b9SJerome Glisse
r100_irq_set(struct radeon_device * rdev)7227ed220d7SMichel Dänzer int r100_irq_set(struct radeon_device *rdev)
7237ed220d7SMichel Dänzer {
7247ed220d7SMichel Dänzer uint32_t tmp = 0;
7257ed220d7SMichel Dänzer
726003e69f9SJerome Glisse if (!rdev->irq.installed) {
727fce7d61bSJoe Perches WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
728003e69f9SJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0);
729003e69f9SJerome Glisse return -EINVAL;
730003e69f9SJerome Glisse }
731736fc37fSChristian Koenig if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7327ed220d7SMichel Dänzer tmp |= RADEON_SW_INT_ENABLE;
7337ed220d7SMichel Dänzer }
7346f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0] ||
735736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[0])) {
7367ed220d7SMichel Dänzer tmp |= RADEON_CRTC_VBLANK_MASK;
7377ed220d7SMichel Dänzer }
7386f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1] ||
739736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[1])) {
7407ed220d7SMichel Dänzer tmp |= RADEON_CRTC2_VBLANK_MASK;
7417ed220d7SMichel Dänzer }
74205a05c50SAlex Deucher if (rdev->irq.hpd[0]) {
74305a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_MASK;
74405a05c50SAlex Deucher }
74505a05c50SAlex Deucher if (rdev->irq.hpd[1]) {
74605a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_MASK;
74705a05c50SAlex Deucher }
7487ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_CNTL, tmp);
749f957063fSAlex Deucher
750f957063fSAlex Deucher /* read back to post the write */
751f957063fSAlex Deucher RREG32(RADEON_GEN_INT_CNTL);
752f957063fSAlex Deucher
7537ed220d7SMichel Dänzer return 0;
7547ed220d7SMichel Dänzer }
7557ed220d7SMichel Dänzer
r100_irq_disable(struct radeon_device * rdev)7569f022ddfSJerome Glisse void r100_irq_disable(struct radeon_device *rdev)
7579f022ddfSJerome Glisse {
7589f022ddfSJerome Glisse u32 tmp;
7599f022ddfSJerome Glisse
7609f022ddfSJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0);
7619f022ddfSJerome Glisse /* Wait and acknowledge irq */
7629f022ddfSJerome Glisse mdelay(1);
7639f022ddfSJerome Glisse tmp = RREG32(R_000044_GEN_INT_STATUS);
7649f022ddfSJerome Glisse WREG32(R_000044_GEN_INT_STATUS, tmp);
7659f022ddfSJerome Glisse }
7669f022ddfSJerome Glisse
r100_irq_ack(struct radeon_device * rdev)767cbdd4501SAndi Kleen static uint32_t r100_irq_ack(struct radeon_device *rdev)
7687ed220d7SMichel Dänzer {
7697ed220d7SMichel Dänzer uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
77005a05c50SAlex Deucher uint32_t irq_mask = RADEON_SW_INT_TEST |
77105a05c50SAlex Deucher RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
77205a05c50SAlex Deucher RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7737ed220d7SMichel Dänzer
7747ed220d7SMichel Dänzer if (irqs) {
7757ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_STATUS, irqs);
7767ed220d7SMichel Dänzer }
7777ed220d7SMichel Dänzer return irqs & irq_mask;
7787ed220d7SMichel Dänzer }
7797ed220d7SMichel Dänzer
r100_irq_process(struct radeon_device * rdev)7807ed220d7SMichel Dänzer int r100_irq_process(struct radeon_device *rdev)
7817ed220d7SMichel Dänzer {
7823e5cb98dSAlex Deucher uint32_t status, msi_rearm;
783d4877cf2SAlex Deucher bool queue_hotplug = false;
7847ed220d7SMichel Dänzer
7857ed220d7SMichel Dänzer status = r100_irq_ack(rdev);
7867ed220d7SMichel Dänzer if (!status) {
7877ed220d7SMichel Dänzer return IRQ_NONE;
7887ed220d7SMichel Dänzer }
789a513c184SJerome Glisse if (rdev->shutdown) {
790a513c184SJerome Glisse return IRQ_NONE;
791a513c184SJerome Glisse }
7927ed220d7SMichel Dänzer while (status) {
7937ed220d7SMichel Dänzer /* SW interrupt */
7947ed220d7SMichel Dänzer if (status & RADEON_SW_INT_TEST) {
7957465280cSAlex Deucher radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7967ed220d7SMichel Dänzer }
7977ed220d7SMichel Dänzer /* Vertical blank interrupts */
7987ed220d7SMichel Dänzer if (status & RADEON_CRTC_VBLANK_STAT) {
7996f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0]) {
800*5e3a0f77SWu Hoi Pok drm_handle_vblank(rdev_to_drm(rdev), 0);
801839461d3SRafał Miłecki rdev->pm.vblank_sync = true;
80273a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue);
8037ed220d7SMichel Dänzer }
804736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[0]))
8051a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 0);
8066f34be50SAlex Deucher }
8077ed220d7SMichel Dänzer if (status & RADEON_CRTC2_VBLANK_STAT) {
8086f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1]) {
809*5e3a0f77SWu Hoi Pok drm_handle_vblank(rdev_to_drm(rdev), 1);
810839461d3SRafał Miłecki rdev->pm.vblank_sync = true;
81173a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue);
8127ed220d7SMichel Dänzer }
813736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[1]))
8141a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 1);
8156f34be50SAlex Deucher }
81605a05c50SAlex Deucher if (status & RADEON_FP_DETECT_STAT) {
817d4877cf2SAlex Deucher queue_hotplug = true;
818d4877cf2SAlex Deucher DRM_DEBUG("HPD1\n");
81905a05c50SAlex Deucher }
82005a05c50SAlex Deucher if (status & RADEON_FP2_DETECT_STAT) {
821d4877cf2SAlex Deucher queue_hotplug = true;
822d4877cf2SAlex Deucher DRM_DEBUG("HPD2\n");
82305a05c50SAlex Deucher }
8247ed220d7SMichel Dänzer status = r100_irq_ack(rdev);
8257ed220d7SMichel Dänzer }
826d4877cf2SAlex Deucher if (queue_hotplug)
827cb5d4166SLyude schedule_delayed_work(&rdev->hotplug_work, 0);
8283e5cb98dSAlex Deucher if (rdev->msi_enabled) {
8293e5cb98dSAlex Deucher switch (rdev->family) {
8303e5cb98dSAlex Deucher case CHIP_RS400:
8313e5cb98dSAlex Deucher case CHIP_RS480:
8323e5cb98dSAlex Deucher msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
8333e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm);
8343e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
8353e5cb98dSAlex Deucher break;
8363e5cb98dSAlex Deucher default:
837b7f5b7deSAlex Deucher WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
8383e5cb98dSAlex Deucher break;
8393e5cb98dSAlex Deucher }
8403e5cb98dSAlex Deucher }
8417ed220d7SMichel Dänzer return IRQ_HANDLED;
8427ed220d7SMichel Dänzer }
8437ed220d7SMichel Dänzer
r100_get_vblank_counter(struct radeon_device * rdev,int crtc)8447ed220d7SMichel Dänzer u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
8457ed220d7SMichel Dänzer {
8467ed220d7SMichel Dänzer if (crtc == 0)
8477ed220d7SMichel Dänzer return RREG32(RADEON_CRTC_CRNT_FRAME);
8487ed220d7SMichel Dänzer else
8497ed220d7SMichel Dänzer return RREG32(RADEON_CRTC2_CRNT_FRAME);
8507ed220d7SMichel Dänzer }
8517ed220d7SMichel Dänzer
852897eba82SMichel Dänzer /**
853897eba82SMichel Dänzer * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
8540d8357c2SLee Jones * @rdev: radeon device structure
8550d8357c2SLee Jones * @ring: ring buffer struct for emitting packets
856897eba82SMichel Dänzer */
r100_ring_hdp_flush(struct radeon_device * rdev,struct radeon_ring * ring)857897eba82SMichel Dänzer static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
858897eba82SMichel Dänzer {
859897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
860897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
861897eba82SMichel Dänzer RADEON_HDP_READ_BUFFER_INVALIDATE);
862897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
863897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
864897eba82SMichel Dänzer }
865897eba82SMichel Dänzer
8669e5b2af7SPauli Nieminen /* Who ever call radeon_fence_emit should call ring_lock and ask
8679e5b2af7SPauli Nieminen * for enough space (today caller are ib schedule and buffer move) */
r100_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)868771fe6b9SJerome Glisse void r100_fence_ring_emit(struct radeon_device *rdev,
869771fe6b9SJerome Glisse struct radeon_fence *fence)
870771fe6b9SJerome Glisse {
871e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[fence->ring];
8727b1f2485SChristian König
8739e5b2af7SPauli Nieminen /* We have to make sure that caches are flushed before
8749e5b2af7SPauli Nieminen * CPU might read something from VRAM. */
875e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
876e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
877e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
878e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
879771fe6b9SJerome Glisse /* Wait until IDLE & CLEAN */
880e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
881e32eb50dSChristian König radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
88272a9987eSMichel Dänzer r100_ring_hdp_flush(rdev, ring);
883771fe6b9SJerome Glisse /* Emit fence sequence & fire IRQ */
884e32eb50dSChristian König radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
885e32eb50dSChristian König radeon_ring_write(ring, fence->seq);
886e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
887e32eb50dSChristian König radeon_ring_write(ring, RADEON_SW_INT_FIRE);
888771fe6b9SJerome Glisse }
889771fe6b9SJerome Glisse
r100_semaphore_ring_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)8901654b817SChristian König bool r100_semaphore_ring_emit(struct radeon_device *rdev,
891e32eb50dSChristian König struct radeon_ring *ring,
89215d3332fSChristian König struct radeon_semaphore *semaphore,
8937b1f2485SChristian König bool emit_wait)
89415d3332fSChristian König {
89515d3332fSChristian König /* Unused on older asics, since we don't have semaphores or multiple rings */
89615d3332fSChristian König BUG();
8971654b817SChristian König return false;
89815d3332fSChristian König }
89915d3332fSChristian König
r100_copy_blit(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct dma_resv * resv)90057d20a43SChristian König struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
901771fe6b9SJerome Glisse uint64_t src_offset,
902771fe6b9SJerome Glisse uint64_t dst_offset,
903003cefe0SAlex Deucher unsigned num_gpu_pages,
90452791eeeSChristian König struct dma_resv *resv)
905771fe6b9SJerome Glisse {
906e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
90757d20a43SChristian König struct radeon_fence *fence;
908771fe6b9SJerome Glisse uint32_t cur_pages;
909003cefe0SAlex Deucher uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
910771fe6b9SJerome Glisse uint32_t pitch;
911771fe6b9SJerome Glisse uint32_t stride_pixels;
912771fe6b9SJerome Glisse unsigned ndw;
913771fe6b9SJerome Glisse int num_loops;
914771fe6b9SJerome Glisse int r = 0;
915771fe6b9SJerome Glisse
916771fe6b9SJerome Glisse /* radeon limited to 16k stride */
917771fe6b9SJerome Glisse stride_bytes &= 0x3fff;
918771fe6b9SJerome Glisse /* radeon pitch is /64 */
919771fe6b9SJerome Glisse pitch = stride_bytes / 64;
920771fe6b9SJerome Glisse stride_pixels = stride_bytes / 4;
921003cefe0SAlex Deucher num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
922771fe6b9SJerome Glisse
923771fe6b9SJerome Glisse /* Ask for enough room for blit + flush + fence */
924771fe6b9SJerome Glisse ndw = 64 + (10 * num_loops);
925e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, ndw);
926771fe6b9SJerome Glisse if (r) {
927771fe6b9SJerome Glisse DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
92857d20a43SChristian König return ERR_PTR(-EINVAL);
929771fe6b9SJerome Glisse }
930003cefe0SAlex Deucher while (num_gpu_pages > 0) {
931003cefe0SAlex Deucher cur_pages = num_gpu_pages;
932771fe6b9SJerome Glisse if (cur_pages > 8191) {
933771fe6b9SJerome Glisse cur_pages = 8191;
934771fe6b9SJerome Glisse }
935003cefe0SAlex Deucher num_gpu_pages -= cur_pages;
936771fe6b9SJerome Glisse
937771fe6b9SJerome Glisse /* pages are in Y direction - height
938771fe6b9SJerome Glisse page width in X direction - width */
939e32eb50dSChristian König radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
940e32eb50dSChristian König radeon_ring_write(ring,
941771fe6b9SJerome Glisse RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
942771fe6b9SJerome Glisse RADEON_GMC_DST_PITCH_OFFSET_CNTL |
943771fe6b9SJerome Glisse RADEON_GMC_SRC_CLIPPING |
944771fe6b9SJerome Glisse RADEON_GMC_DST_CLIPPING |
945771fe6b9SJerome Glisse RADEON_GMC_BRUSH_NONE |
946771fe6b9SJerome Glisse (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
947771fe6b9SJerome Glisse RADEON_GMC_SRC_DATATYPE_COLOR |
948771fe6b9SJerome Glisse RADEON_ROP3_S |
949771fe6b9SJerome Glisse RADEON_DP_SRC_SOURCE_MEMORY |
950771fe6b9SJerome Glisse RADEON_GMC_CLR_CMP_CNTL_DIS |
951771fe6b9SJerome Glisse RADEON_GMC_WR_MSK_DIS);
952e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
953e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
954e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
955e32eb50dSChristian König radeon_ring_write(ring, 0);
956e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
957e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages);
958e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages);
959e32eb50dSChristian König radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
960771fe6b9SJerome Glisse }
961e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
962e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
963e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
964e32eb50dSChristian König radeon_ring_write(ring,
965771fe6b9SJerome Glisse RADEON_WAIT_2D_IDLECLEAN |
966771fe6b9SJerome Glisse RADEON_WAIT_HOST_IDLECLEAN |
967771fe6b9SJerome Glisse RADEON_WAIT_DMA_GUI_IDLE);
96857d20a43SChristian König r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
96957d20a43SChristian König if (r) {
97057d20a43SChristian König radeon_ring_unlock_undo(rdev, ring);
97157d20a43SChristian König return ERR_PTR(r);
972771fe6b9SJerome Glisse }
9731538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false);
97457d20a43SChristian König return fence;
975771fe6b9SJerome Glisse }
976771fe6b9SJerome Glisse
r100_cp_wait_for_idle(struct radeon_device * rdev)97745600232SJerome Glisse static int r100_cp_wait_for_idle(struct radeon_device *rdev)
97845600232SJerome Glisse {
97945600232SJerome Glisse unsigned i;
98045600232SJerome Glisse u32 tmp;
98145600232SJerome Glisse
98245600232SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
98345600232SJerome Glisse tmp = RREG32(R_000E40_RBBM_STATUS);
98445600232SJerome Glisse if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
98545600232SJerome Glisse return 0;
98645600232SJerome Glisse }
98745600232SJerome Glisse udelay(1);
98845600232SJerome Glisse }
98945600232SJerome Glisse return -1;
99045600232SJerome Glisse }
99145600232SJerome Glisse
r100_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)992f712812eSAlex Deucher void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
993771fe6b9SJerome Glisse {
994771fe6b9SJerome Glisse int r;
995771fe6b9SJerome Glisse
996e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2);
997771fe6b9SJerome Glisse if (r) {
998771fe6b9SJerome Glisse return;
999771fe6b9SJerome Glisse }
1000e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
1001e32eb50dSChristian König radeon_ring_write(ring,
1002771fe6b9SJerome Glisse RADEON_ISYNC_ANY2D_IDLE3D |
1003771fe6b9SJerome Glisse RADEON_ISYNC_ANY3D_IDLE2D |
1004771fe6b9SJerome Glisse RADEON_ISYNC_WAIT_IDLEGUI |
1005771fe6b9SJerome Glisse RADEON_ISYNC_CPSCRATCH_IDLEGUI);
10061538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false);
1007771fe6b9SJerome Glisse }
1008771fe6b9SJerome Glisse
100970967ab9SBen Hutchings
101070967ab9SBen Hutchings /* Load the microcode for the CP */
r100_cp_init_microcode(struct radeon_device * rdev)101170967ab9SBen Hutchings static int r100_cp_init_microcode(struct radeon_device *rdev)
1012771fe6b9SJerome Glisse {
101370967ab9SBen Hutchings const char *fw_name = NULL;
101470967ab9SBen Hutchings int err;
1015771fe6b9SJerome Glisse
1016d9fdaafbSDave Airlie DRM_DEBUG_KMS("\n");
101770967ab9SBen Hutchings
1018c474a1a7SGeert Uytterhoeven switch (rdev->family) {
1019c474a1a7SGeert Uytterhoeven case CHIP_R100:
1020c474a1a7SGeert Uytterhoeven case CHIP_RV100:
1021c474a1a7SGeert Uytterhoeven case CHIP_RV200:
1022c474a1a7SGeert Uytterhoeven case CHIP_RS100:
1023c474a1a7SGeert Uytterhoeven case CHIP_RS200:
1024771fe6b9SJerome Glisse DRM_INFO("Loading R100 Microcode\n");
102570967ab9SBen Hutchings fw_name = FIRMWARE_R100;
1026c474a1a7SGeert Uytterhoeven break;
1027c474a1a7SGeert Uytterhoeven
1028c474a1a7SGeert Uytterhoeven case CHIP_R200:
1029c474a1a7SGeert Uytterhoeven case CHIP_RV250:
1030c474a1a7SGeert Uytterhoeven case CHIP_RV280:
1031c474a1a7SGeert Uytterhoeven case CHIP_RS300:
1032771fe6b9SJerome Glisse DRM_INFO("Loading R200 Microcode\n");
103370967ab9SBen Hutchings fw_name = FIRMWARE_R200;
1034c474a1a7SGeert Uytterhoeven break;
1035c474a1a7SGeert Uytterhoeven
1036c474a1a7SGeert Uytterhoeven case CHIP_R300:
1037c474a1a7SGeert Uytterhoeven case CHIP_R350:
1038c474a1a7SGeert Uytterhoeven case CHIP_RV350:
1039c474a1a7SGeert Uytterhoeven case CHIP_RV380:
1040c474a1a7SGeert Uytterhoeven case CHIP_RS400:
1041c474a1a7SGeert Uytterhoeven case CHIP_RS480:
1042771fe6b9SJerome Glisse DRM_INFO("Loading R300 Microcode\n");
104370967ab9SBen Hutchings fw_name = FIRMWARE_R300;
1044c474a1a7SGeert Uytterhoeven break;
1045c474a1a7SGeert Uytterhoeven
1046c474a1a7SGeert Uytterhoeven case CHIP_R420:
1047c474a1a7SGeert Uytterhoeven case CHIP_R423:
1048c474a1a7SGeert Uytterhoeven case CHIP_RV410:
1049771fe6b9SJerome Glisse DRM_INFO("Loading R400 Microcode\n");
105070967ab9SBen Hutchings fw_name = FIRMWARE_R420;
1051c474a1a7SGeert Uytterhoeven break;
1052c474a1a7SGeert Uytterhoeven
1053c474a1a7SGeert Uytterhoeven case CHIP_RS690:
1054c474a1a7SGeert Uytterhoeven case CHIP_RS740:
1055771fe6b9SJerome Glisse DRM_INFO("Loading RS690/RS740 Microcode\n");
105670967ab9SBen Hutchings fw_name = FIRMWARE_RS690;
1057c474a1a7SGeert Uytterhoeven break;
1058c474a1a7SGeert Uytterhoeven
1059c474a1a7SGeert Uytterhoeven case CHIP_RS600:
1060771fe6b9SJerome Glisse DRM_INFO("Loading RS600 Microcode\n");
106170967ab9SBen Hutchings fw_name = FIRMWARE_RS600;
1062c474a1a7SGeert Uytterhoeven break;
1063c474a1a7SGeert Uytterhoeven
1064c474a1a7SGeert Uytterhoeven case CHIP_RV515:
1065c474a1a7SGeert Uytterhoeven case CHIP_R520:
1066c474a1a7SGeert Uytterhoeven case CHIP_RV530:
1067c474a1a7SGeert Uytterhoeven case CHIP_R580:
1068c474a1a7SGeert Uytterhoeven case CHIP_RV560:
1069c474a1a7SGeert Uytterhoeven case CHIP_RV570:
1070771fe6b9SJerome Glisse DRM_INFO("Loading R500 Microcode\n");
107170967ab9SBen Hutchings fw_name = FIRMWARE_R520;
1072c474a1a7SGeert Uytterhoeven break;
1073c474a1a7SGeert Uytterhoeven
1074c474a1a7SGeert Uytterhoeven default:
1075c474a1a7SGeert Uytterhoeven DRM_ERROR("Unsupported Radeon family %u\n", rdev->family);
1076c474a1a7SGeert Uytterhoeven return -EINVAL;
107770967ab9SBen Hutchings }
107870967ab9SBen Hutchings
10790a168933SJerome Glisse err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
108070967ab9SBen Hutchings if (err) {
10817ca85295SJoe Perches pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
10823ce0a23dSJerome Glisse } else if (rdev->me_fw->size % 8) {
10837ca85295SJoe Perches pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
10843ce0a23dSJerome Glisse rdev->me_fw->size, fw_name);
108570967ab9SBen Hutchings err = -EINVAL;
10863ce0a23dSJerome Glisse release_firmware(rdev->me_fw);
10873ce0a23dSJerome Glisse rdev->me_fw = NULL;
108870967ab9SBen Hutchings }
108970967ab9SBen Hutchings return err;
109070967ab9SBen Hutchings }
1091d4550907SJerome Glisse
r100_gfx_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)1092ea31bf69SAlex Deucher u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1093ea31bf69SAlex Deucher struct radeon_ring *ring)
1094ea31bf69SAlex Deucher {
1095ea31bf69SAlex Deucher u32 rptr;
1096ea31bf69SAlex Deucher
1097ea31bf69SAlex Deucher if (rdev->wb.enabled)
1098ea31bf69SAlex Deucher rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1099ea31bf69SAlex Deucher else
1100ea31bf69SAlex Deucher rptr = RREG32(RADEON_CP_RB_RPTR);
1101ea31bf69SAlex Deucher
1102ea31bf69SAlex Deucher return rptr;
1103ea31bf69SAlex Deucher }
1104ea31bf69SAlex Deucher
r100_gfx_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1105ea31bf69SAlex Deucher u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1106ea31bf69SAlex Deucher struct radeon_ring *ring)
1107ea31bf69SAlex Deucher {
11080003b8d2SMasahiro Yamada return RREG32(RADEON_CP_RB_WPTR);
1109ea31bf69SAlex Deucher }
1110ea31bf69SAlex Deucher
r100_gfx_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1111ea31bf69SAlex Deucher void r100_gfx_set_wptr(struct radeon_device *rdev,
1112ea31bf69SAlex Deucher struct radeon_ring *ring)
1113ea31bf69SAlex Deucher {
1114ea31bf69SAlex Deucher WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1115ea31bf69SAlex Deucher (void)RREG32(RADEON_CP_RB_WPTR);
1116ea31bf69SAlex Deucher }
1117ea31bf69SAlex Deucher
r100_cp_load_microcode(struct radeon_device * rdev)111870967ab9SBen Hutchings static void r100_cp_load_microcode(struct radeon_device *rdev)
111970967ab9SBen Hutchings {
112070967ab9SBen Hutchings const __be32 *fw_data;
112170967ab9SBen Hutchings int i, size;
112270967ab9SBen Hutchings
112370967ab9SBen Hutchings if (r100_gui_wait_for_idle(rdev)) {
11247ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
112570967ab9SBen Hutchings }
112670967ab9SBen Hutchings
11273ce0a23dSJerome Glisse if (rdev->me_fw) {
11283ce0a23dSJerome Glisse size = rdev->me_fw->size / 4;
11293ce0a23dSJerome Glisse fw_data = (const __be32 *)&rdev->me_fw->data[0];
113070967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_ADDR, 0);
113170967ab9SBen Hutchings for (i = 0; i < size; i += 2) {
113270967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAH,
113370967ab9SBen Hutchings be32_to_cpup(&fw_data[i]));
113470967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAL,
113570967ab9SBen Hutchings be32_to_cpup(&fw_data[i + 1]));
1136771fe6b9SJerome Glisse }
1137771fe6b9SJerome Glisse }
1138771fe6b9SJerome Glisse }
1139771fe6b9SJerome Glisse
r100_cp_init(struct radeon_device * rdev,unsigned ring_size)1140771fe6b9SJerome Glisse int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1141771fe6b9SJerome Glisse {
1142e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1143771fe6b9SJerome Glisse unsigned rb_bufsz;
1144771fe6b9SJerome Glisse unsigned rb_blksz;
1145771fe6b9SJerome Glisse unsigned max_fetch;
1146771fe6b9SJerome Glisse unsigned pre_write_timer;
1147771fe6b9SJerome Glisse unsigned pre_write_limit;
1148771fe6b9SJerome Glisse unsigned indirect2_start;
1149771fe6b9SJerome Glisse unsigned indirect1_start;
1150771fe6b9SJerome Glisse uint32_t tmp;
1151771fe6b9SJerome Glisse int r;
1152771fe6b9SJerome Glisse
11535b54d679SNirmoy Das r100_debugfs_cp_init(rdev);
11543ce0a23dSJerome Glisse if (!rdev->me_fw) {
115570967ab9SBen Hutchings r = r100_cp_init_microcode(rdev);
115670967ab9SBen Hutchings if (r) {
115770967ab9SBen Hutchings DRM_ERROR("Failed to load firmware!\n");
115870967ab9SBen Hutchings return r;
115970967ab9SBen Hutchings }
116070967ab9SBen Hutchings }
116170967ab9SBen Hutchings
1162771fe6b9SJerome Glisse /* Align ring size */
1163b72a8925SDaniel Vetter rb_bufsz = order_base_2(ring_size / 8);
1164771fe6b9SJerome Glisse ring_size = (1 << (rb_bufsz + 1)) * 4;
1165771fe6b9SJerome Glisse r100_cp_load_microcode(rdev);
1166e32eb50dSChristian König r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
11672e1e6dadSChristian König RADEON_CP_PACKET2);
1168771fe6b9SJerome Glisse if (r) {
1169771fe6b9SJerome Glisse return r;
1170771fe6b9SJerome Glisse }
1171771fe6b9SJerome Glisse /* Each time the cp read 1024 bytes (16 dword/quadword) update
1172771fe6b9SJerome Glisse * the rptr copy in system ram */
1173771fe6b9SJerome Glisse rb_blksz = 9;
1174771fe6b9SJerome Glisse /* cp will read 128bytes at a time (4 dwords) */
1175771fe6b9SJerome Glisse max_fetch = 1;
1176e32eb50dSChristian König ring->align_mask = 16 - 1;
1177771fe6b9SJerome Glisse /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1178771fe6b9SJerome Glisse pre_write_timer = 64;
1179771fe6b9SJerome Glisse /* Force CP_RB_WPTR write if written more than one time before the
1180771fe6b9SJerome Glisse * delay expire
1181771fe6b9SJerome Glisse */
1182771fe6b9SJerome Glisse pre_write_limit = 0;
1183771fe6b9SJerome Glisse /* Setup the cp cache like this (cache size is 96 dwords) :
1184771fe6b9SJerome Glisse * RING 0 to 15
1185771fe6b9SJerome Glisse * INDIRECT1 16 to 79
1186771fe6b9SJerome Glisse * INDIRECT2 80 to 95
1187771fe6b9SJerome Glisse * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1188771fe6b9SJerome Glisse * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1189771fe6b9SJerome Glisse * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1190771fe6b9SJerome Glisse * Idea being that most of the gpu cmd will be through indirect1 buffer
1191771fe6b9SJerome Glisse * so it gets the bigger cache.
1192771fe6b9SJerome Glisse */
1193771fe6b9SJerome Glisse indirect2_start = 80;
1194771fe6b9SJerome Glisse indirect1_start = 16;
1195771fe6b9SJerome Glisse /* cp setup */
1196771fe6b9SJerome Glisse WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1197d6f28938SAlex Deucher tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1198771fe6b9SJerome Glisse REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1199724c80e1SAlex Deucher REG_SET(RADEON_MAX_FETCH, max_fetch));
1200d6f28938SAlex Deucher #ifdef __BIG_ENDIAN
1201d6f28938SAlex Deucher tmp |= RADEON_BUF_SWAP_32BIT;
1202d6f28938SAlex Deucher #endif
1203724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1204d6f28938SAlex Deucher
1205771fe6b9SJerome Glisse /* Set ring address */
1206e32eb50dSChristian König DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1207e32eb50dSChristian König WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1208771fe6b9SJerome Glisse /* Force read & write ptr to 0 */
1209724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1210771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0);
1211e32eb50dSChristian König ring->wptr = 0;
1212e32eb50dSChristian König WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1213724c80e1SAlex Deucher
1214724c80e1SAlex Deucher /* set the wb address whether it's enabled or not */
1215724c80e1SAlex Deucher WREG32(R_00070C_CP_RB_RPTR_ADDR,
1216724c80e1SAlex Deucher S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1217724c80e1SAlex Deucher WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1218724c80e1SAlex Deucher
1219724c80e1SAlex Deucher if (rdev->wb.enabled)
1220724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0xff);
1221724c80e1SAlex Deucher else {
1222724c80e1SAlex Deucher tmp |= RADEON_RB_NO_UPDATE;
1223724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0);
1224724c80e1SAlex Deucher }
1225724c80e1SAlex Deucher
1226771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp);
1227771fe6b9SJerome Glisse udelay(10);
1228771fe6b9SJerome Glisse /* Set cp mode to bus mastering & enable cp*/
1229771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE,
1230771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1231771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1232d75ee3beSAlex Deucher WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1233d75ee3beSAlex Deucher WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1234771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
12352099810fSDave Airlie
12362099810fSDave Airlie /* at this point everything should be setup correctly to enable master */
12372099810fSDave Airlie pci_set_master(rdev->pdev);
12382099810fSDave Airlie
1239f712812eSAlex Deucher radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1240f712812eSAlex Deucher r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1241771fe6b9SJerome Glisse if (r) {
1242771fe6b9SJerome Glisse DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1243771fe6b9SJerome Glisse return r;
1244771fe6b9SJerome Glisse }
1245e32eb50dSChristian König ring->ready = true;
124653595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1247c7eff978SAlex Deucher
124816c58081SSimon Kitching if (!ring->rptr_save_reg /* not resuming from suspend */
124916c58081SSimon Kitching && radeon_ring_supports_scratch_reg(rdev, ring)) {
1250c7eff978SAlex Deucher r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1251c7eff978SAlex Deucher if (r) {
1252c7eff978SAlex Deucher DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1253c7eff978SAlex Deucher ring->rptr_save_reg = 0;
1254c7eff978SAlex Deucher }
1255c7eff978SAlex Deucher }
1256771fe6b9SJerome Glisse return 0;
1257771fe6b9SJerome Glisse }
1258771fe6b9SJerome Glisse
r100_cp_fini(struct radeon_device * rdev)1259771fe6b9SJerome Glisse void r100_cp_fini(struct radeon_device *rdev)
1260771fe6b9SJerome Glisse {
126145600232SJerome Glisse if (r100_cp_wait_for_idle(rdev)) {
126245600232SJerome Glisse DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
126345600232SJerome Glisse }
1264771fe6b9SJerome Glisse /* Disable ring */
1265a18d7ea1SJerome Glisse r100_cp_disable(rdev);
1266c7eff978SAlex Deucher radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1267e32eb50dSChristian König radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1268771fe6b9SJerome Glisse DRM_INFO("radeon: cp finalized\n");
1269771fe6b9SJerome Glisse }
1270771fe6b9SJerome Glisse
r100_cp_disable(struct radeon_device * rdev)1271771fe6b9SJerome Glisse void r100_cp_disable(struct radeon_device *rdev)
1272771fe6b9SJerome Glisse {
1273771fe6b9SJerome Glisse /* Disable ring */
127453595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1275e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1276771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 0);
1277771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0);
1278724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0);
1279771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) {
12807ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1281771fe6b9SJerome Glisse }
1282771fe6b9SJerome Glisse }
1283771fe6b9SJerome Glisse
1284771fe6b9SJerome Glisse /*
1285771fe6b9SJerome Glisse * CS functions
1286771fe6b9SJerome Glisse */
r100_reloc_pitch_offset(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)12870242f74dSAlex Deucher int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
12880242f74dSAlex Deucher struct radeon_cs_packet *pkt,
12890242f74dSAlex Deucher unsigned idx,
12900242f74dSAlex Deucher unsigned reg)
12910242f74dSAlex Deucher {
12920242f74dSAlex Deucher int r;
12930242f74dSAlex Deucher u32 tile_flags = 0;
12940242f74dSAlex Deucher u32 tmp;
12951d0c0942SChristian König struct radeon_bo_list *reloc;
12960242f74dSAlex Deucher u32 value;
12970242f74dSAlex Deucher
1298012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
12990242f74dSAlex Deucher if (r) {
13000242f74dSAlex Deucher DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
13010242f74dSAlex Deucher idx, reg);
1302c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13030242f74dSAlex Deucher return r;
13040242f74dSAlex Deucher }
13050242f74dSAlex Deucher
13060242f74dSAlex Deucher value = radeon_get_ib_value(p, idx);
13070242f74dSAlex Deucher tmp = value & 0x003fffff;
1308df0af440SChristian König tmp += (((u32)reloc->gpu_offset) >> 10);
13090242f74dSAlex Deucher
13100242f74dSAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1311df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO)
13120242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MACRO;
1313df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) {
13140242f74dSAlex Deucher if (reg == RADEON_SRC_PITCH_OFFSET) {
13150242f74dSAlex Deucher DRM_ERROR("Cannot src blit from microtiled surface\n");
1316c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13170242f74dSAlex Deucher return -EINVAL;
13180242f74dSAlex Deucher }
13190242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MICRO;
13200242f74dSAlex Deucher }
13210242f74dSAlex Deucher
13220242f74dSAlex Deucher tmp |= tile_flags;
13230242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
13240242f74dSAlex Deucher } else
13250242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
13260242f74dSAlex Deucher return 0;
13270242f74dSAlex Deucher }
13280242f74dSAlex Deucher
r100_packet3_load_vbpntr(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,int idx)13290242f74dSAlex Deucher int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
13300242f74dSAlex Deucher struct radeon_cs_packet *pkt,
13310242f74dSAlex Deucher int idx)
13320242f74dSAlex Deucher {
13330242f74dSAlex Deucher unsigned c, i;
13341d0c0942SChristian König struct radeon_bo_list *reloc;
13350242f74dSAlex Deucher struct r100_cs_track *track;
13360242f74dSAlex Deucher int r = 0;
13370242f74dSAlex Deucher volatile uint32_t *ib;
13380242f74dSAlex Deucher u32 idx_value;
13390242f74dSAlex Deucher
13400242f74dSAlex Deucher ib = p->ib.ptr;
13410242f74dSAlex Deucher track = (struct r100_cs_track *)p->track;
13420242f74dSAlex Deucher c = radeon_get_ib_value(p, idx++) & 0x1F;
13430242f74dSAlex Deucher if (c > 16) {
13440242f74dSAlex Deucher DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
13450242f74dSAlex Deucher pkt->opcode);
1346c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13470242f74dSAlex Deucher return -EINVAL;
13480242f74dSAlex Deucher }
13490242f74dSAlex Deucher track->num_arrays = c;
13500242f74dSAlex Deucher for (i = 0; i < (c - 1); i+=2, idx+=3) {
1351012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
13520242f74dSAlex Deucher if (r) {
13530242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n",
13540242f74dSAlex Deucher pkt->opcode);
1355c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13560242f74dSAlex Deucher return r;
13570242f74dSAlex Deucher }
13580242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx);
1359df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
13600242f74dSAlex Deucher
13610242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8;
13620242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj;
13630242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F;
1364012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
13650242f74dSAlex Deucher if (r) {
13660242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n",
13670242f74dSAlex Deucher pkt->opcode);
1368c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13690242f74dSAlex Deucher return r;
13700242f74dSAlex Deucher }
1371df0af440SChristian König ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
13720242f74dSAlex Deucher track->arrays[i + 1].robj = reloc->robj;
13730242f74dSAlex Deucher track->arrays[i + 1].esize = idx_value >> 24;
13740242f74dSAlex Deucher track->arrays[i + 1].esize &= 0x7F;
13750242f74dSAlex Deucher }
13760242f74dSAlex Deucher if (c & 1) {
1377012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
13780242f74dSAlex Deucher if (r) {
13790242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n",
13800242f74dSAlex Deucher pkt->opcode);
1381c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
13820242f74dSAlex Deucher return r;
13830242f74dSAlex Deucher }
13840242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx);
1385df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
13860242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj;
13870242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8;
13880242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F;
13890242f74dSAlex Deucher }
13900242f74dSAlex Deucher return r;
13910242f74dSAlex Deucher }
13920242f74dSAlex Deucher
r100_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,const unsigned * auth,unsigned n,radeon_packet0_check_t check)1393771fe6b9SJerome Glisse int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1394771fe6b9SJerome Glisse struct radeon_cs_packet *pkt,
1395068a117cSJerome Glisse const unsigned *auth, unsigned n,
1396771fe6b9SJerome Glisse radeon_packet0_check_t check)
1397771fe6b9SJerome Glisse {
1398771fe6b9SJerome Glisse unsigned reg;
1399771fe6b9SJerome Glisse unsigned i, j, m;
1400771fe6b9SJerome Glisse unsigned idx;
1401771fe6b9SJerome Glisse int r;
1402771fe6b9SJerome Glisse
1403771fe6b9SJerome Glisse idx = pkt->idx + 1;
1404771fe6b9SJerome Glisse reg = pkt->reg;
1405068a117cSJerome Glisse /* Check that register fall into register range
1406068a117cSJerome Glisse * determined by the number of entry (n) in the
1407068a117cSJerome Glisse * safe register bitmap.
1408068a117cSJerome Glisse */
1409771fe6b9SJerome Glisse if (pkt->one_reg_wr) {
1410771fe6b9SJerome Glisse if ((reg >> 7) > n) {
1411771fe6b9SJerome Glisse return -EINVAL;
1412771fe6b9SJerome Glisse }
1413771fe6b9SJerome Glisse } else {
1414771fe6b9SJerome Glisse if (((reg + (pkt->count << 2)) >> 7) > n) {
1415771fe6b9SJerome Glisse return -EINVAL;
1416771fe6b9SJerome Glisse }
1417771fe6b9SJerome Glisse }
1418771fe6b9SJerome Glisse for (i = 0; i <= pkt->count; i++, idx++) {
1419771fe6b9SJerome Glisse j = (reg >> 7);
1420771fe6b9SJerome Glisse m = 1 << ((reg >> 2) & 31);
1421771fe6b9SJerome Glisse if (auth[j] & m) {
1422771fe6b9SJerome Glisse r = check(p, pkt, idx, reg);
1423771fe6b9SJerome Glisse if (r) {
1424771fe6b9SJerome Glisse return r;
1425771fe6b9SJerome Glisse }
1426771fe6b9SJerome Glisse }
1427771fe6b9SJerome Glisse if (pkt->one_reg_wr) {
1428771fe6b9SJerome Glisse if (!(auth[j] & m)) {
1429771fe6b9SJerome Glisse break;
1430771fe6b9SJerome Glisse }
1431771fe6b9SJerome Glisse } else {
1432771fe6b9SJerome Glisse reg += 4;
1433771fe6b9SJerome Glisse }
1434771fe6b9SJerome Glisse }
1435771fe6b9SJerome Glisse return 0;
1436771fe6b9SJerome Glisse }
1437771fe6b9SJerome Glisse
1438771fe6b9SJerome Glisse /**
1439463e2989SLee Jones * r100_cs_packet_parse_vline() - parse userspace VLINE packet
14400d8357c2SLee Jones * @p: parser structure holding parsing context.
1441531369e6SDave Airlie *
1442531369e6SDave Airlie * Userspace sends a special sequence for VLINE waits.
1443531369e6SDave Airlie * PACKET0 - VLINE_START_END + value
1444531369e6SDave Airlie * PACKET0 - WAIT_UNTIL +_value
1445531369e6SDave Airlie * RELOC (P3) - crtc_id in reloc.
1446531369e6SDave Airlie *
1447531369e6SDave Airlie * This function parses this and relocates the VLINE START END
1448531369e6SDave Airlie * and WAIT UNTIL packets to the correct crtc.
1449531369e6SDave Airlie * It also detects a switched off crtc and nulls out the
1450531369e6SDave Airlie * wait in that case.
1451531369e6SDave Airlie */
r100_cs_packet_parse_vline(struct radeon_cs_parser * p)1452531369e6SDave Airlie int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1453531369e6SDave Airlie {
1454531369e6SDave Airlie struct drm_crtc *crtc;
1455531369e6SDave Airlie struct radeon_crtc *radeon_crtc;
1456531369e6SDave Airlie struct radeon_cs_packet p3reloc, waitreloc;
1457531369e6SDave Airlie int crtc_id;
1458531369e6SDave Airlie int r;
1459531369e6SDave Airlie uint32_t header, h_idx, reg;
1460513bcb46SDave Airlie volatile uint32_t *ib;
1461531369e6SDave Airlie
1462f2e39221SJerome Glisse ib = p->ib.ptr;
1463531369e6SDave Airlie
1464531369e6SDave Airlie /* parse the wait until */
1465c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1466531369e6SDave Airlie if (r)
1467531369e6SDave Airlie return r;
1468531369e6SDave Airlie
1469531369e6SDave Airlie /* check its a wait until and only 1 count */
1470531369e6SDave Airlie if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1471531369e6SDave Airlie waitreloc.count != 0) {
1472531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until segment\n");
1473a3a88a66SPaul Bolle return -EINVAL;
1474531369e6SDave Airlie }
1475531369e6SDave Airlie
1476513bcb46SDave Airlie if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1477531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until\n");
1478a3a88a66SPaul Bolle return -EINVAL;
1479531369e6SDave Airlie }
1480531369e6SDave Airlie
1481531369e6SDave Airlie /* jump over the NOP */
1482c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1483531369e6SDave Airlie if (r)
1484531369e6SDave Airlie return r;
1485531369e6SDave Airlie
1486531369e6SDave Airlie h_idx = p->idx - 2;
148790ebd065SAlex Deucher p->idx += waitreloc.count + 2;
148890ebd065SAlex Deucher p->idx += p3reloc.count + 2;
1489531369e6SDave Airlie
1490513bcb46SDave Airlie header = radeon_get_ib_value(p, h_idx);
1491513bcb46SDave Airlie crtc_id = radeon_get_ib_value(p, h_idx + 5);
14924e872ae2SIlija Hadzic reg = R100_CP_PACKET0_GET_REG(header);
1493*5e3a0f77SWu Hoi Pok crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id);
1494b957f457SRob Clark if (!crtc) {
1495531369e6SDave Airlie DRM_ERROR("cannot find crtc %d\n", crtc_id);
149610e10d34SVille Syrjälä return -ENOENT;
1497531369e6SDave Airlie }
1498531369e6SDave Airlie radeon_crtc = to_radeon_crtc(crtc);
1499531369e6SDave Airlie crtc_id = radeon_crtc->crtc_id;
1500531369e6SDave Airlie
1501531369e6SDave Airlie if (!crtc->enabled) {
1502531369e6SDave Airlie /* if the CRTC isn't enabled - we need to nop out the wait until */
1503513bcb46SDave Airlie ib[h_idx + 2] = PACKET2(0);
1504513bcb46SDave Airlie ib[h_idx + 3] = PACKET2(0);
1505531369e6SDave Airlie } else if (crtc_id == 1) {
1506531369e6SDave Airlie switch (reg) {
1507531369e6SDave Airlie case AVIVO_D1MODE_VLINE_START_END:
150890ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK;
1509531369e6SDave Airlie header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1510531369e6SDave Airlie break;
1511531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE:
151290ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK;
1513531369e6SDave Airlie header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1514531369e6SDave Airlie break;
1515531369e6SDave Airlie default:
1516531369e6SDave Airlie DRM_ERROR("unknown crtc reloc\n");
1517a3a88a66SPaul Bolle return -EINVAL;
1518531369e6SDave Airlie }
1519513bcb46SDave Airlie ib[h_idx] = header;
1520513bcb46SDave Airlie ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1521531369e6SDave Airlie }
1522a3a88a66SPaul Bolle
1523a3a88a66SPaul Bolle return 0;
1524531369e6SDave Airlie }
1525531369e6SDave Airlie
r100_get_vtx_size(uint32_t vtx_fmt)1526551ebd83SDave Airlie static int r100_get_vtx_size(uint32_t vtx_fmt)
1527551ebd83SDave Airlie {
1528551ebd83SDave Airlie int vtx_size;
1529551ebd83SDave Airlie vtx_size = 2;
1530551ebd83SDave Airlie /* ordered according to bits in spec */
1531551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1532551ebd83SDave Airlie vtx_size++;
1533551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1534551ebd83SDave Airlie vtx_size += 3;
1535551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1536551ebd83SDave Airlie vtx_size++;
1537551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1538551ebd83SDave Airlie vtx_size++;
1539551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1540551ebd83SDave Airlie vtx_size += 3;
1541551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1542551ebd83SDave Airlie vtx_size++;
1543551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1544551ebd83SDave Airlie vtx_size++;
1545551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1546551ebd83SDave Airlie vtx_size += 2;
1547551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1548551ebd83SDave Airlie vtx_size += 2;
1549551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1550551ebd83SDave Airlie vtx_size++;
1551551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1552551ebd83SDave Airlie vtx_size += 2;
1553551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1554551ebd83SDave Airlie vtx_size++;
1555551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1556551ebd83SDave Airlie vtx_size += 2;
1557551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1558551ebd83SDave Airlie vtx_size++;
1559551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1560551ebd83SDave Airlie vtx_size++;
1561551ebd83SDave Airlie /* blend weight */
1562551ebd83SDave Airlie if (vtx_fmt & (0x7 << 15))
1563551ebd83SDave Airlie vtx_size += (vtx_fmt >> 15) & 0x7;
1564551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1565551ebd83SDave Airlie vtx_size += 3;
1566551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1567551ebd83SDave Airlie vtx_size += 2;
1568551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1569551ebd83SDave Airlie vtx_size++;
1570551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1571551ebd83SDave Airlie vtx_size++;
1572551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1573551ebd83SDave Airlie vtx_size++;
1574551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1575551ebd83SDave Airlie vtx_size++;
1576551ebd83SDave Airlie return vtx_size;
1577551ebd83SDave Airlie }
1578551ebd83SDave Airlie
r100_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1579771fe6b9SJerome Glisse static int r100_packet0_check(struct radeon_cs_parser *p,
1580551ebd83SDave Airlie struct radeon_cs_packet *pkt,
1581551ebd83SDave Airlie unsigned idx, unsigned reg)
1582771fe6b9SJerome Glisse {
15831d0c0942SChristian König struct radeon_bo_list *reloc;
1584551ebd83SDave Airlie struct r100_cs_track *track;
1585771fe6b9SJerome Glisse volatile uint32_t *ib;
1586771fe6b9SJerome Glisse uint32_t tmp;
1587771fe6b9SJerome Glisse int r;
1588551ebd83SDave Airlie int i, face;
1589e024e110SDave Airlie u32 tile_flags = 0;
1590513bcb46SDave Airlie u32 idx_value;
1591771fe6b9SJerome Glisse
1592f2e39221SJerome Glisse ib = p->ib.ptr;
1593551ebd83SDave Airlie track = (struct r100_cs_track *)p->track;
1594551ebd83SDave Airlie
1595513bcb46SDave Airlie idx_value = radeon_get_ib_value(p, idx);
1596513bcb46SDave Airlie
1597771fe6b9SJerome Glisse switch (reg) {
1598531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE:
1599531369e6SDave Airlie r = r100_cs_packet_parse_vline(p);
1600531369e6SDave Airlie if (r) {
1601531369e6SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1602531369e6SDave Airlie idx, reg);
1603c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1604531369e6SDave Airlie return r;
1605531369e6SDave Airlie }
1606531369e6SDave Airlie break;
1607771fe6b9SJerome Glisse /* FIXME: only allow PACKET3 blit? easier to check for out of
1608771fe6b9SJerome Glisse * range access */
1609771fe6b9SJerome Glisse case RADEON_DST_PITCH_OFFSET:
1610771fe6b9SJerome Glisse case RADEON_SRC_PITCH_OFFSET:
1611551ebd83SDave Airlie r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1612551ebd83SDave Airlie if (r)
1613551ebd83SDave Airlie return r;
1614551ebd83SDave Airlie break;
1615551ebd83SDave Airlie case RADEON_RB3D_DEPTHOFFSET:
1616012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1617771fe6b9SJerome Glisse if (r) {
1618771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1619771fe6b9SJerome Glisse idx, reg);
1620c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1621771fe6b9SJerome Glisse return r;
1622771fe6b9SJerome Glisse }
1623551ebd83SDave Airlie track->zb.robj = reloc->robj;
1624513bcb46SDave Airlie track->zb.offset = idx_value;
162540b4a759SMarek Olšák track->zb_dirty = true;
1626df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1627771fe6b9SJerome Glisse break;
1628771fe6b9SJerome Glisse case RADEON_RB3D_COLOROFFSET:
1629012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1630551ebd83SDave Airlie if (r) {
1631551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1632551ebd83SDave Airlie idx, reg);
1633c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1634551ebd83SDave Airlie return r;
1635551ebd83SDave Airlie }
1636551ebd83SDave Airlie track->cb[0].robj = reloc->robj;
1637513bcb46SDave Airlie track->cb[0].offset = idx_value;
163840b4a759SMarek Olšák track->cb_dirty = true;
1639df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1640551ebd83SDave Airlie break;
1641771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_0:
1642771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_1:
1643771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_2:
1644551ebd83SDave Airlie i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1645012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1646771fe6b9SJerome Glisse if (r) {
1647771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1648771fe6b9SJerome Glisse idx, reg);
1649c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1650771fe6b9SJerome Glisse return r;
1651771fe6b9SJerome Glisse }
1652f2746f83SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1653df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO)
1654f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MACRO_TILE;
1655df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO)
1656f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1657f2746f83SAlex Deucher
1658f2746f83SAlex Deucher tmp = idx_value & ~(0x7 << 2);
1659f2746f83SAlex Deucher tmp |= tile_flags;
1660df0af440SChristian König ib[idx] = tmp + ((u32)reloc->gpu_offset);
1661f2746f83SAlex Deucher } else
1662df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1663551ebd83SDave Airlie track->textures[i].robj = reloc->robj;
166440b4a759SMarek Olšák track->tex_dirty = true;
1665771fe6b9SJerome Glisse break;
1666551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_0:
1667551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_1:
1668551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_2:
1669551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_3:
1670551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_4:
1671551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1672012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1673551ebd83SDave Airlie if (r) {
1674551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1675551ebd83SDave Airlie idx, reg);
1676c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1677551ebd83SDave Airlie return r;
1678551ebd83SDave Airlie }
1679513bcb46SDave Airlie track->textures[0].cube_info[i].offset = idx_value;
1680df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1681551ebd83SDave Airlie track->textures[0].cube_info[i].robj = reloc->robj;
168240b4a759SMarek Olšák track->tex_dirty = true;
1683551ebd83SDave Airlie break;
1684551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_0:
1685551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_1:
1686551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_2:
1687551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_3:
1688551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_4:
1689551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1690012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1691551ebd83SDave Airlie if (r) {
1692551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1693551ebd83SDave Airlie idx, reg);
1694c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1695551ebd83SDave Airlie return r;
1696551ebd83SDave Airlie }
1697513bcb46SDave Airlie track->textures[1].cube_info[i].offset = idx_value;
1698df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1699551ebd83SDave Airlie track->textures[1].cube_info[i].robj = reloc->robj;
170040b4a759SMarek Olšák track->tex_dirty = true;
1701551ebd83SDave Airlie break;
1702551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_0:
1703551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_1:
1704551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_2:
1705551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_3:
1706551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_4:
1707551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1708012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1709551ebd83SDave Airlie if (r) {
1710551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1711551ebd83SDave Airlie idx, reg);
1712c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1713551ebd83SDave Airlie return r;
1714551ebd83SDave Airlie }
1715513bcb46SDave Airlie track->textures[2].cube_info[i].offset = idx_value;
1716df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1717551ebd83SDave Airlie track->textures[2].cube_info[i].robj = reloc->robj;
171840b4a759SMarek Olšák track->tex_dirty = true;
1719551ebd83SDave Airlie break;
1720551ebd83SDave Airlie case RADEON_RE_WIDTH_HEIGHT:
1721513bcb46SDave Airlie track->maxy = ((idx_value >> 16) & 0x7FF);
172240b4a759SMarek Olšák track->cb_dirty = true;
172340b4a759SMarek Olšák track->zb_dirty = true;
1724551ebd83SDave Airlie break;
1725e024e110SDave Airlie case RADEON_RB3D_COLORPITCH:
1726012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1727e024e110SDave Airlie if (r) {
1728e024e110SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1729e024e110SDave Airlie idx, reg);
1730c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1731e024e110SDave Airlie return r;
1732e024e110SDave Airlie }
1733c9068eb2SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1734df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO)
1735e024e110SDave Airlie tile_flags |= RADEON_COLOR_TILE_ENABLE;
1736df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO)
1737e024e110SDave Airlie tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1738e024e110SDave Airlie
1739513bcb46SDave Airlie tmp = idx_value & ~(0x7 << 16);
1740e024e110SDave Airlie tmp |= tile_flags;
1741e024e110SDave Airlie ib[idx] = tmp;
1742c9068eb2SAlex Deucher } else
1743c9068eb2SAlex Deucher ib[idx] = idx_value;
1744551ebd83SDave Airlie
1745513bcb46SDave Airlie track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
174640b4a759SMarek Olšák track->cb_dirty = true;
1747551ebd83SDave Airlie break;
1748551ebd83SDave Airlie case RADEON_RB3D_DEPTHPITCH:
1749513bcb46SDave Airlie track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
175040b4a759SMarek Olšák track->zb_dirty = true;
1751551ebd83SDave Airlie break;
1752551ebd83SDave Airlie case RADEON_RB3D_CNTL:
1753513bcb46SDave Airlie switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1754551ebd83SDave Airlie case 7:
1755551ebd83SDave Airlie case 8:
1756551ebd83SDave Airlie case 9:
1757551ebd83SDave Airlie case 11:
1758551ebd83SDave Airlie case 12:
1759551ebd83SDave Airlie track->cb[0].cpp = 1;
1760551ebd83SDave Airlie break;
1761551ebd83SDave Airlie case 3:
1762551ebd83SDave Airlie case 4:
1763551ebd83SDave Airlie case 15:
1764551ebd83SDave Airlie track->cb[0].cpp = 2;
1765551ebd83SDave Airlie break;
1766551ebd83SDave Airlie case 6:
1767551ebd83SDave Airlie track->cb[0].cpp = 4;
1768551ebd83SDave Airlie break;
1769551ebd83SDave Airlie default:
1770551ebd83SDave Airlie DRM_ERROR("Invalid color buffer format (%d) !\n",
1771513bcb46SDave Airlie ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1772551ebd83SDave Airlie return -EINVAL;
1773551ebd83SDave Airlie }
1774513bcb46SDave Airlie track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
177540b4a759SMarek Olšák track->cb_dirty = true;
177640b4a759SMarek Olšák track->zb_dirty = true;
1777551ebd83SDave Airlie break;
1778551ebd83SDave Airlie case RADEON_RB3D_ZSTENCILCNTL:
1779513bcb46SDave Airlie switch (idx_value & 0xf) {
1780551ebd83SDave Airlie case 0:
1781551ebd83SDave Airlie track->zb.cpp = 2;
1782551ebd83SDave Airlie break;
1783551ebd83SDave Airlie case 2:
1784551ebd83SDave Airlie case 3:
1785551ebd83SDave Airlie case 4:
1786551ebd83SDave Airlie case 5:
1787551ebd83SDave Airlie case 9:
1788551ebd83SDave Airlie case 11:
1789551ebd83SDave Airlie track->zb.cpp = 4;
1790551ebd83SDave Airlie break;
1791551ebd83SDave Airlie default:
1792551ebd83SDave Airlie break;
1793551ebd83SDave Airlie }
179440b4a759SMarek Olšák track->zb_dirty = true;
1795e024e110SDave Airlie break;
179617782d99SDave Airlie case RADEON_RB3D_ZPASS_ADDR:
1797012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
179817782d99SDave Airlie if (r) {
179917782d99SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
180017782d99SDave Airlie idx, reg);
1801c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
180217782d99SDave Airlie return r;
180317782d99SDave Airlie }
1804df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset);
180517782d99SDave Airlie break;
1806551ebd83SDave Airlie case RADEON_PP_CNTL:
1807551ebd83SDave Airlie {
1808513bcb46SDave Airlie uint32_t temp = idx_value >> 4;
1809551ebd83SDave Airlie for (i = 0; i < track->num_texture; i++)
1810551ebd83SDave Airlie track->textures[i].enabled = !!(temp & (1 << i));
181140b4a759SMarek Olšák track->tex_dirty = true;
1812551ebd83SDave Airlie }
1813551ebd83SDave Airlie break;
1814551ebd83SDave Airlie case RADEON_SE_VF_CNTL:
1815513bcb46SDave Airlie track->vap_vf_cntl = idx_value;
1816551ebd83SDave Airlie break;
1817551ebd83SDave Airlie case RADEON_SE_VTX_FMT:
1818513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(idx_value);
1819551ebd83SDave Airlie break;
1820551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_0:
1821551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_1:
1822551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_2:
1823551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1824513bcb46SDave Airlie track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1825513bcb46SDave Airlie track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
182640b4a759SMarek Olšák track->tex_dirty = true;
1827551ebd83SDave Airlie break;
1828551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_0:
1829551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_1:
1830551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_2:
1831551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1832513bcb46SDave Airlie track->textures[i].pitch = idx_value + 32;
183340b4a759SMarek Olšák track->tex_dirty = true;
1834551ebd83SDave Airlie break;
1835551ebd83SDave Airlie case RADEON_PP_TXFILTER_0:
1836551ebd83SDave Airlie case RADEON_PP_TXFILTER_1:
1837551ebd83SDave Airlie case RADEON_PP_TXFILTER_2:
1838551ebd83SDave Airlie i = (reg - RADEON_PP_TXFILTER_0) / 24;
1839513bcb46SDave Airlie track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1840551ebd83SDave Airlie >> RADEON_MAX_MIP_LEVEL_SHIFT);
1841513bcb46SDave Airlie tmp = (idx_value >> 23) & 0x7;
1842551ebd83SDave Airlie if (tmp == 2 || tmp == 6)
1843551ebd83SDave Airlie track->textures[i].roundup_w = false;
1844513bcb46SDave Airlie tmp = (idx_value >> 27) & 0x7;
1845551ebd83SDave Airlie if (tmp == 2 || tmp == 6)
1846551ebd83SDave Airlie track->textures[i].roundup_h = false;
184740b4a759SMarek Olšák track->tex_dirty = true;
1848551ebd83SDave Airlie break;
1849551ebd83SDave Airlie case RADEON_PP_TXFORMAT_0:
1850551ebd83SDave Airlie case RADEON_PP_TXFORMAT_1:
1851551ebd83SDave Airlie case RADEON_PP_TXFORMAT_2:
1852551ebd83SDave Airlie i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1853513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
18547bf2f607Szhengbin track->textures[i].use_pitch = true;
1855551ebd83SDave Airlie } else {
18567bf2f607Szhengbin track->textures[i].use_pitch = false;
1857008037d4SAlex Deucher track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1858008037d4SAlex Deucher track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1859551ebd83SDave Airlie }
1860513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1861551ebd83SDave Airlie track->textures[i].tex_coord_type = 2;
1862513bcb46SDave Airlie switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1863551ebd83SDave Airlie case RADEON_TXFORMAT_I8:
1864551ebd83SDave Airlie case RADEON_TXFORMAT_RGB332:
1865551ebd83SDave Airlie case RADEON_TXFORMAT_Y8:
1866551ebd83SDave Airlie track->textures[i].cpp = 1;
1867f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1868551ebd83SDave Airlie break;
1869551ebd83SDave Airlie case RADEON_TXFORMAT_AI88:
1870551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB1555:
1871551ebd83SDave Airlie case RADEON_TXFORMAT_RGB565:
1872551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB4444:
1873551ebd83SDave Airlie case RADEON_TXFORMAT_VYUY422:
1874551ebd83SDave Airlie case RADEON_TXFORMAT_YVYU422:
1875551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW16:
1876551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDV655:
1877551ebd83SDave Airlie case RADEON_TXFORMAT_DUDV88:
1878551ebd83SDave Airlie track->textures[i].cpp = 2;
1879f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1880551ebd83SDave Airlie break;
1881551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB8888:
1882551ebd83SDave Airlie case RADEON_TXFORMAT_RGBA8888:
1883551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW32:
1884551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDUV8888:
1885551ebd83SDave Airlie track->textures[i].cpp = 4;
1886f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1887551ebd83SDave Airlie break;
1888d785d78bSDave Airlie case RADEON_TXFORMAT_DXT1:
1889d785d78bSDave Airlie track->textures[i].cpp = 1;
1890d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1891d785d78bSDave Airlie break;
1892d785d78bSDave Airlie case RADEON_TXFORMAT_DXT23:
1893d785d78bSDave Airlie case RADEON_TXFORMAT_DXT45:
1894d785d78bSDave Airlie track->textures[i].cpp = 1;
1895d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1896d785d78bSDave Airlie break;
1897551ebd83SDave Airlie }
1898513bcb46SDave Airlie track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1899513bcb46SDave Airlie track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
190040b4a759SMarek Olšák track->tex_dirty = true;
1901551ebd83SDave Airlie break;
1902551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_0:
1903551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_1:
1904551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_2:
1905513bcb46SDave Airlie tmp = idx_value;
1906551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1907551ebd83SDave Airlie for (face = 0; face < 4; face++) {
1908551ebd83SDave Airlie track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1909551ebd83SDave Airlie track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1910551ebd83SDave Airlie }
191140b4a759SMarek Olšák track->tex_dirty = true;
1912551ebd83SDave Airlie break;
1913771fe6b9SJerome Glisse default:
19147ca85295SJoe Perches pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1915551ebd83SDave Airlie return -EINVAL;
1916771fe6b9SJerome Glisse }
1917771fe6b9SJerome Glisse return 0;
1918771fe6b9SJerome Glisse }
1919771fe6b9SJerome Glisse
r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,struct radeon_bo * robj)1920068a117cSJerome Glisse int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1921068a117cSJerome Glisse struct radeon_cs_packet *pkt,
19224c788679SJerome Glisse struct radeon_bo *robj)
1923068a117cSJerome Glisse {
1924068a117cSJerome Glisse unsigned idx;
1925513bcb46SDave Airlie u32 value;
1926068a117cSJerome Glisse idx = pkt->idx + 1;
1927513bcb46SDave Airlie value = radeon_get_ib_value(p, idx + 2);
19284c788679SJerome Glisse if ((value + 1) > radeon_bo_size(robj)) {
1929068a117cSJerome Glisse DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1930068a117cSJerome Glisse "(need %u have %lu) !\n",
1931513bcb46SDave Airlie value + 1,
19324c788679SJerome Glisse radeon_bo_size(robj));
1933068a117cSJerome Glisse return -EINVAL;
1934068a117cSJerome Glisse }
1935068a117cSJerome Glisse return 0;
1936068a117cSJerome Glisse }
1937068a117cSJerome Glisse
r100_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1938771fe6b9SJerome Glisse static int r100_packet3_check(struct radeon_cs_parser *p,
1939771fe6b9SJerome Glisse struct radeon_cs_packet *pkt)
1940771fe6b9SJerome Glisse {
19411d0c0942SChristian König struct radeon_bo_list *reloc;
1942551ebd83SDave Airlie struct r100_cs_track *track;
1943771fe6b9SJerome Glisse unsigned idx;
1944771fe6b9SJerome Glisse volatile uint32_t *ib;
1945771fe6b9SJerome Glisse int r;
1946771fe6b9SJerome Glisse
1947f2e39221SJerome Glisse ib = p->ib.ptr;
1948771fe6b9SJerome Glisse idx = pkt->idx + 1;
1949551ebd83SDave Airlie track = (struct r100_cs_track *)p->track;
1950771fe6b9SJerome Glisse switch (pkt->opcode) {
1951771fe6b9SJerome Glisse case PACKET3_3D_LOAD_VBPNTR:
1952513bcb46SDave Airlie r = r100_packet3_load_vbpntr(p, pkt, idx);
1953513bcb46SDave Airlie if (r)
1954771fe6b9SJerome Glisse return r;
1955771fe6b9SJerome Glisse break;
1956771fe6b9SJerome Glisse case PACKET3_INDX_BUFFER:
1957012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1958771fe6b9SJerome Glisse if (r) {
1959771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1960c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1961771fe6b9SJerome Glisse return r;
1962771fe6b9SJerome Glisse }
1963df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1964068a117cSJerome Glisse r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1965068a117cSJerome Glisse if (r) {
1966068a117cSJerome Glisse return r;
1967068a117cSJerome Glisse }
1968771fe6b9SJerome Glisse break;
1969771fe6b9SJerome Glisse case 0x23:
1970771fe6b9SJerome Glisse /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1971012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1972771fe6b9SJerome Glisse if (r) {
1973771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1974c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt);
1975771fe6b9SJerome Glisse return r;
1976771fe6b9SJerome Glisse }
1977df0af440SChristian König ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1978551ebd83SDave Airlie track->num_arrays = 1;
1979513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1980551ebd83SDave Airlie
1981551ebd83SDave Airlie track->arrays[0].robj = reloc->robj;
1982551ebd83SDave Airlie track->arrays[0].esize = track->vtx_size;
1983551ebd83SDave Airlie
1984513bcb46SDave Airlie track->max_indx = radeon_get_ib_value(p, idx+1);
1985551ebd83SDave Airlie
1986513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1987551ebd83SDave Airlie track->immd_dwords = pkt->count - 1;
1988551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
1989551ebd83SDave Airlie if (r)
1990551ebd83SDave Airlie return r;
1991771fe6b9SJerome Glisse break;
1992771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD:
1993513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1994551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1995551ebd83SDave Airlie return -EINVAL;
1996551ebd83SDave Airlie }
1997cf57fc7aSAlex Deucher track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1998513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1999551ebd83SDave Airlie track->immd_dwords = pkt->count - 1;
2000551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2001551ebd83SDave Airlie if (r)
2002551ebd83SDave Airlie return r;
2003551ebd83SDave Airlie break;
2004771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */
2005771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD_2:
2006513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
2007551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2008551ebd83SDave Airlie return -EINVAL;
2009551ebd83SDave Airlie }
2010513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2011551ebd83SDave Airlie track->immd_dwords = pkt->count;
2012551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2013551ebd83SDave Airlie if (r)
2014551ebd83SDave Airlie return r;
2015551ebd83SDave Airlie break;
2016771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */
2017771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF_2:
2018513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2019551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2020551ebd83SDave Airlie if (r)
2021551ebd83SDave Airlie return r;
2022551ebd83SDave Airlie break;
2023771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */
2024771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX_2:
2025513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2026551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2027551ebd83SDave Airlie if (r)
2028551ebd83SDave Airlie return r;
2029551ebd83SDave Airlie break;
2030771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */
2031771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF:
2032513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2033551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2034551ebd83SDave Airlie if (r)
2035551ebd83SDave Airlie return r;
2036551ebd83SDave Airlie break;
2037771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */
2038771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX:
2039513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2040551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track);
2041551ebd83SDave Airlie if (r)
2042551ebd83SDave Airlie return r;
2043551ebd83SDave Airlie break;
2044771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */
2045ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_HIZ:
2046ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_ZMASK:
2047ab9e1f59SDave Airlie if (p->rdev->hyperz_filp != p->filp)
2048ab9e1f59SDave Airlie return -EINVAL;
2049ab9e1f59SDave Airlie break;
2050771fe6b9SJerome Glisse case PACKET3_NOP:
2051771fe6b9SJerome Glisse break;
2052771fe6b9SJerome Glisse default:
2053771fe6b9SJerome Glisse DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2054771fe6b9SJerome Glisse return -EINVAL;
2055771fe6b9SJerome Glisse }
2056771fe6b9SJerome Glisse return 0;
2057771fe6b9SJerome Glisse }
2058771fe6b9SJerome Glisse
r100_cs_parse(struct radeon_cs_parser * p)2059771fe6b9SJerome Glisse int r100_cs_parse(struct radeon_cs_parser *p)
2060771fe6b9SJerome Glisse {
2061771fe6b9SJerome Glisse struct radeon_cs_packet pkt;
20629f022ddfSJerome Glisse struct r100_cs_track *track;
2063771fe6b9SJerome Glisse int r;
2064771fe6b9SJerome Glisse
20659f022ddfSJerome Glisse track = kzalloc(sizeof(*track), GFP_KERNEL);
2066ce067913SDan Carpenter if (!track)
2067ce067913SDan Carpenter return -ENOMEM;
20689f022ddfSJerome Glisse r100_cs_track_clear(p->rdev, track);
20699f022ddfSJerome Glisse p->track = track;
2070771fe6b9SJerome Glisse do {
2071c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &pkt, p->idx);
2072771fe6b9SJerome Glisse if (r) {
2073771fe6b9SJerome Glisse return r;
2074771fe6b9SJerome Glisse }
2075771fe6b9SJerome Glisse p->idx += pkt.count + 2;
2076771fe6b9SJerome Glisse switch (pkt.type) {
20774e872ae2SIlija Hadzic case RADEON_PACKET_TYPE0:
2078551ebd83SDave Airlie if (p->rdev->family >= CHIP_R200)
2079551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt,
2080551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm,
2081551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size,
2082551ebd83SDave Airlie &r200_packet0_check);
2083551ebd83SDave Airlie else
2084551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt,
2085551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm,
2086551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size,
2087551ebd83SDave Airlie &r100_packet0_check);
2088771fe6b9SJerome Glisse break;
20894e872ae2SIlija Hadzic case RADEON_PACKET_TYPE2:
2090771fe6b9SJerome Glisse break;
20914e872ae2SIlija Hadzic case RADEON_PACKET_TYPE3:
2092771fe6b9SJerome Glisse r = r100_packet3_check(p, &pkt);
2093771fe6b9SJerome Glisse break;
2094771fe6b9SJerome Glisse default:
2095771fe6b9SJerome Glisse DRM_ERROR("Unknown packet type %d !\n",
2096771fe6b9SJerome Glisse pkt.type);
2097771fe6b9SJerome Glisse return -EINVAL;
2098771fe6b9SJerome Glisse }
209966b3543eSIlija Hadzic if (r)
2100771fe6b9SJerome Glisse return r;
21016d2d13ddSChristian König } while (p->idx < p->chunk_ib->length_dw);
2102771fe6b9SJerome Glisse return 0;
2103771fe6b9SJerome Glisse }
2104771fe6b9SJerome Glisse
r100_cs_track_texture_print(struct r100_cs_track_texture * t)21050242f74dSAlex Deucher static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
21060242f74dSAlex Deucher {
21070242f74dSAlex Deucher DRM_ERROR("pitch %d\n", t->pitch);
21080242f74dSAlex Deucher DRM_ERROR("use_pitch %d\n", t->use_pitch);
21090242f74dSAlex Deucher DRM_ERROR("width %d\n", t->width);
21100242f74dSAlex Deucher DRM_ERROR("width_11 %d\n", t->width_11);
21110242f74dSAlex Deucher DRM_ERROR("height %d\n", t->height);
21120242f74dSAlex Deucher DRM_ERROR("height_11 %d\n", t->height_11);
21130242f74dSAlex Deucher DRM_ERROR("num levels %d\n", t->num_levels);
21140242f74dSAlex Deucher DRM_ERROR("depth %d\n", t->txdepth);
21150242f74dSAlex Deucher DRM_ERROR("bpp %d\n", t->cpp);
21160242f74dSAlex Deucher DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
21170242f74dSAlex Deucher DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
21180242f74dSAlex Deucher DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
21190242f74dSAlex Deucher DRM_ERROR("compress format %d\n", t->compress_format);
21200242f74dSAlex Deucher }
21210242f74dSAlex Deucher
r100_track_compress_size(int compress_format,int w,int h)21220242f74dSAlex Deucher static int r100_track_compress_size(int compress_format, int w, int h)
21230242f74dSAlex Deucher {
21240242f74dSAlex Deucher int block_width, block_height, block_bytes;
21250242f74dSAlex Deucher int wblocks, hblocks;
21260242f74dSAlex Deucher int min_wblocks;
21270242f74dSAlex Deucher int sz;
21280242f74dSAlex Deucher
21290242f74dSAlex Deucher block_width = 4;
21300242f74dSAlex Deucher block_height = 4;
21310242f74dSAlex Deucher
21320242f74dSAlex Deucher switch (compress_format) {
21330242f74dSAlex Deucher case R100_TRACK_COMP_DXT1:
21340242f74dSAlex Deucher block_bytes = 8;
21350242f74dSAlex Deucher min_wblocks = 4;
21360242f74dSAlex Deucher break;
21370242f74dSAlex Deucher default:
21380242f74dSAlex Deucher case R100_TRACK_COMP_DXT35:
21390242f74dSAlex Deucher block_bytes = 16;
21400242f74dSAlex Deucher min_wblocks = 2;
21410242f74dSAlex Deucher break;
21420242f74dSAlex Deucher }
21430242f74dSAlex Deucher
21440242f74dSAlex Deucher hblocks = (h + block_height - 1) / block_height;
21450242f74dSAlex Deucher wblocks = (w + block_width - 1) / block_width;
21460242f74dSAlex Deucher if (wblocks < min_wblocks)
21470242f74dSAlex Deucher wblocks = min_wblocks;
21480242f74dSAlex Deucher sz = wblocks * hblocks * block_bytes;
21490242f74dSAlex Deucher return sz;
21500242f74dSAlex Deucher }
21510242f74dSAlex Deucher
r100_cs_track_cube(struct radeon_device * rdev,struct r100_cs_track * track,unsigned idx)21520242f74dSAlex Deucher static int r100_cs_track_cube(struct radeon_device *rdev,
21530242f74dSAlex Deucher struct r100_cs_track *track, unsigned idx)
21540242f74dSAlex Deucher {
21550242f74dSAlex Deucher unsigned face, w, h;
21560242f74dSAlex Deucher struct radeon_bo *cube_robj;
21570242f74dSAlex Deucher unsigned long size;
21580242f74dSAlex Deucher unsigned compress_format = track->textures[idx].compress_format;
21590242f74dSAlex Deucher
21600242f74dSAlex Deucher for (face = 0; face < 5; face++) {
21610242f74dSAlex Deucher cube_robj = track->textures[idx].cube_info[face].robj;
21620242f74dSAlex Deucher w = track->textures[idx].cube_info[face].width;
21630242f74dSAlex Deucher h = track->textures[idx].cube_info[face].height;
21640242f74dSAlex Deucher
21650242f74dSAlex Deucher if (compress_format) {
21660242f74dSAlex Deucher size = r100_track_compress_size(compress_format, w, h);
21670242f74dSAlex Deucher } else
21680242f74dSAlex Deucher size = w * h;
21690242f74dSAlex Deucher size *= track->textures[idx].cpp;
21700242f74dSAlex Deucher
21710242f74dSAlex Deucher size += track->textures[idx].cube_info[face].offset;
21720242f74dSAlex Deucher
21730242f74dSAlex Deucher if (size > radeon_bo_size(cube_robj)) {
21740242f74dSAlex Deucher DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
21750242f74dSAlex Deucher size, radeon_bo_size(cube_robj));
21760242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[idx]);
21770242f74dSAlex Deucher return -1;
21780242f74dSAlex Deucher }
21790242f74dSAlex Deucher }
21800242f74dSAlex Deucher return 0;
21810242f74dSAlex Deucher }
21820242f74dSAlex Deucher
r100_cs_track_texture_check(struct radeon_device * rdev,struct r100_cs_track * track)21830242f74dSAlex Deucher static int r100_cs_track_texture_check(struct radeon_device *rdev,
21840242f74dSAlex Deucher struct r100_cs_track *track)
21850242f74dSAlex Deucher {
21860242f74dSAlex Deucher struct radeon_bo *robj;
21870242f74dSAlex Deucher unsigned long size;
21880242f74dSAlex Deucher unsigned u, i, w, h, d;
21890242f74dSAlex Deucher int ret;
21900242f74dSAlex Deucher
21910242f74dSAlex Deucher for (u = 0; u < track->num_texture; u++) {
21920242f74dSAlex Deucher if (!track->textures[u].enabled)
21930242f74dSAlex Deucher continue;
21940242f74dSAlex Deucher if (track->textures[u].lookup_disable)
21950242f74dSAlex Deucher continue;
21960242f74dSAlex Deucher robj = track->textures[u].robj;
21970242f74dSAlex Deucher if (robj == NULL) {
21980242f74dSAlex Deucher DRM_ERROR("No texture bound to unit %u\n", u);
21990242f74dSAlex Deucher return -EINVAL;
22000242f74dSAlex Deucher }
22010242f74dSAlex Deucher size = 0;
22020242f74dSAlex Deucher for (i = 0; i <= track->textures[u].num_levels; i++) {
22030242f74dSAlex Deucher if (track->textures[u].use_pitch) {
22040242f74dSAlex Deucher if (rdev->family < CHIP_R300)
22050242f74dSAlex Deucher w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
22060242f74dSAlex Deucher else
22070242f74dSAlex Deucher w = track->textures[u].pitch / (1 << i);
22080242f74dSAlex Deucher } else {
22090242f74dSAlex Deucher w = track->textures[u].width;
22100242f74dSAlex Deucher if (rdev->family >= CHIP_RV515)
22110242f74dSAlex Deucher w |= track->textures[u].width_11;
22120242f74dSAlex Deucher w = w / (1 << i);
22130242f74dSAlex Deucher if (track->textures[u].roundup_w)
22140242f74dSAlex Deucher w = roundup_pow_of_two(w);
22150242f74dSAlex Deucher }
22160242f74dSAlex Deucher h = track->textures[u].height;
22170242f74dSAlex Deucher if (rdev->family >= CHIP_RV515)
22180242f74dSAlex Deucher h |= track->textures[u].height_11;
22190242f74dSAlex Deucher h = h / (1 << i);
22200242f74dSAlex Deucher if (track->textures[u].roundup_h)
22210242f74dSAlex Deucher h = roundup_pow_of_two(h);
22220242f74dSAlex Deucher if (track->textures[u].tex_coord_type == 1) {
22230242f74dSAlex Deucher d = (1 << track->textures[u].txdepth) / (1 << i);
22240242f74dSAlex Deucher if (!d)
22250242f74dSAlex Deucher d = 1;
22260242f74dSAlex Deucher } else {
22270242f74dSAlex Deucher d = 1;
22280242f74dSAlex Deucher }
22290242f74dSAlex Deucher if (track->textures[u].compress_format) {
22300242f74dSAlex Deucher
22310242f74dSAlex Deucher size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
22320242f74dSAlex Deucher /* compressed textures are block based */
22330242f74dSAlex Deucher } else
22340242f74dSAlex Deucher size += w * h * d;
22350242f74dSAlex Deucher }
22360242f74dSAlex Deucher size *= track->textures[u].cpp;
22370242f74dSAlex Deucher
22380242f74dSAlex Deucher switch (track->textures[u].tex_coord_type) {
22390242f74dSAlex Deucher case 0:
22400242f74dSAlex Deucher case 1:
22410242f74dSAlex Deucher break;
22420242f74dSAlex Deucher case 2:
22430242f74dSAlex Deucher if (track->separate_cube) {
22440242f74dSAlex Deucher ret = r100_cs_track_cube(rdev, track, u);
22450242f74dSAlex Deucher if (ret)
22460242f74dSAlex Deucher return ret;
22470242f74dSAlex Deucher } else
22480242f74dSAlex Deucher size *= 6;
22490242f74dSAlex Deucher break;
22500242f74dSAlex Deucher default:
22510242f74dSAlex Deucher DRM_ERROR("Invalid texture coordinate type %u for unit "
22520242f74dSAlex Deucher "%u\n", track->textures[u].tex_coord_type, u);
22530242f74dSAlex Deucher return -EINVAL;
22540242f74dSAlex Deucher }
22550242f74dSAlex Deucher if (size > radeon_bo_size(robj)) {
22560242f74dSAlex Deucher DRM_ERROR("Texture of unit %u needs %lu bytes but is "
22570242f74dSAlex Deucher "%lu\n", u, size, radeon_bo_size(robj));
22580242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[u]);
22590242f74dSAlex Deucher return -EINVAL;
22600242f74dSAlex Deucher }
22610242f74dSAlex Deucher }
22620242f74dSAlex Deucher return 0;
22630242f74dSAlex Deucher }
22640242f74dSAlex Deucher
r100_cs_track_check(struct radeon_device * rdev,struct r100_cs_track * track)22650242f74dSAlex Deucher int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
22660242f74dSAlex Deucher {
22670242f74dSAlex Deucher unsigned i;
22680242f74dSAlex Deucher unsigned long size;
22690242f74dSAlex Deucher unsigned prim_walk;
22700242f74dSAlex Deucher unsigned nverts;
22710242f74dSAlex Deucher unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
22720242f74dSAlex Deucher
22730242f74dSAlex Deucher if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
22740242f74dSAlex Deucher !track->blend_read_enable)
22750242f74dSAlex Deucher num_cb = 0;
22760242f74dSAlex Deucher
22770242f74dSAlex Deucher for (i = 0; i < num_cb; i++) {
22780242f74dSAlex Deucher if (track->cb[i].robj == NULL) {
22790242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
22800242f74dSAlex Deucher return -EINVAL;
22810242f74dSAlex Deucher }
22820242f74dSAlex Deucher size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
22830242f74dSAlex Deucher size += track->cb[i].offset;
22840242f74dSAlex Deucher if (size > radeon_bo_size(track->cb[i].robj)) {
22850242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for color buffer %d "
22860242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size,
22870242f74dSAlex Deucher radeon_bo_size(track->cb[i].robj));
22880242f74dSAlex Deucher DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
22890242f74dSAlex Deucher i, track->cb[i].pitch, track->cb[i].cpp,
22900242f74dSAlex Deucher track->cb[i].offset, track->maxy);
22910242f74dSAlex Deucher return -EINVAL;
22920242f74dSAlex Deucher }
22930242f74dSAlex Deucher }
22940242f74dSAlex Deucher track->cb_dirty = false;
22950242f74dSAlex Deucher
22960242f74dSAlex Deucher if (track->zb_dirty && track->z_enabled) {
22970242f74dSAlex Deucher if (track->zb.robj == NULL) {
22980242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for z buffer !\n");
22990242f74dSAlex Deucher return -EINVAL;
23000242f74dSAlex Deucher }
23010242f74dSAlex Deucher size = track->zb.pitch * track->zb.cpp * track->maxy;
23020242f74dSAlex Deucher size += track->zb.offset;
23030242f74dSAlex Deucher if (size > radeon_bo_size(track->zb.robj)) {
23040242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for z buffer "
23050242f74dSAlex Deucher "(need %lu have %lu) !\n", size,
23060242f74dSAlex Deucher radeon_bo_size(track->zb.robj));
23070242f74dSAlex Deucher DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
23080242f74dSAlex Deucher track->zb.pitch, track->zb.cpp,
23090242f74dSAlex Deucher track->zb.offset, track->maxy);
23100242f74dSAlex Deucher return -EINVAL;
23110242f74dSAlex Deucher }
23120242f74dSAlex Deucher }
23130242f74dSAlex Deucher track->zb_dirty = false;
23140242f74dSAlex Deucher
23150242f74dSAlex Deucher if (track->aa_dirty && track->aaresolve) {
23160242f74dSAlex Deucher if (track->aa.robj == NULL) {
23170242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
23180242f74dSAlex Deucher return -EINVAL;
23190242f74dSAlex Deucher }
23200242f74dSAlex Deucher /* I believe the format comes from colorbuffer0. */
23210242f74dSAlex Deucher size = track->aa.pitch * track->cb[0].cpp * track->maxy;
23220242f74dSAlex Deucher size += track->aa.offset;
23230242f74dSAlex Deucher if (size > radeon_bo_size(track->aa.robj)) {
23240242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
23250242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size,
23260242f74dSAlex Deucher radeon_bo_size(track->aa.robj));
23270242f74dSAlex Deucher DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
23280242f74dSAlex Deucher i, track->aa.pitch, track->cb[0].cpp,
23290242f74dSAlex Deucher track->aa.offset, track->maxy);
23300242f74dSAlex Deucher return -EINVAL;
23310242f74dSAlex Deucher }
23320242f74dSAlex Deucher }
23330242f74dSAlex Deucher track->aa_dirty = false;
23340242f74dSAlex Deucher
23350242f74dSAlex Deucher prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
23360242f74dSAlex Deucher if (track->vap_vf_cntl & (1 << 14)) {
23370242f74dSAlex Deucher nverts = track->vap_alt_nverts;
23380242f74dSAlex Deucher } else {
23390242f74dSAlex Deucher nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
23400242f74dSAlex Deucher }
23410242f74dSAlex Deucher switch (prim_walk) {
23420242f74dSAlex Deucher case 1:
23430242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) {
234405648491SNikita Zhandarovich size = track->arrays[i].esize * track->max_indx * 4UL;
23450242f74dSAlex Deucher if (track->arrays[i].robj == NULL) {
23460242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer "
23470242f74dSAlex Deucher "bound\n", prim_walk, i);
23480242f74dSAlex Deucher return -EINVAL;
23490242f74dSAlex Deucher }
23500242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) {
23510242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u "
23520242f74dSAlex Deucher "need %lu dwords have %lu dwords\n",
23530242f74dSAlex Deucher prim_walk, i, size >> 2,
23540242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj)
23550242f74dSAlex Deucher >> 2);
23560242f74dSAlex Deucher DRM_ERROR("Max indices %u\n", track->max_indx);
23570242f74dSAlex Deucher return -EINVAL;
23580242f74dSAlex Deucher }
23590242f74dSAlex Deucher }
23600242f74dSAlex Deucher break;
23610242f74dSAlex Deucher case 2:
23620242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) {
236305648491SNikita Zhandarovich size = track->arrays[i].esize * (nverts - 1) * 4UL;
23640242f74dSAlex Deucher if (track->arrays[i].robj == NULL) {
23650242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer "
23660242f74dSAlex Deucher "bound\n", prim_walk, i);
23670242f74dSAlex Deucher return -EINVAL;
23680242f74dSAlex Deucher }
23690242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) {
23700242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u "
23710242f74dSAlex Deucher "need %lu dwords have %lu dwords\n",
23720242f74dSAlex Deucher prim_walk, i, size >> 2,
23730242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj)
23740242f74dSAlex Deucher >> 2);
23750242f74dSAlex Deucher return -EINVAL;
23760242f74dSAlex Deucher }
23770242f74dSAlex Deucher }
23780242f74dSAlex Deucher break;
23790242f74dSAlex Deucher case 3:
23800242f74dSAlex Deucher size = track->vtx_size * nverts;
23810242f74dSAlex Deucher if (size != track->immd_dwords) {
23820242f74dSAlex Deucher DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
23830242f74dSAlex Deucher track->immd_dwords, size);
23840242f74dSAlex Deucher DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
23850242f74dSAlex Deucher nverts, track->vtx_size);
23860242f74dSAlex Deucher return -EINVAL;
23870242f74dSAlex Deucher }
23880242f74dSAlex Deucher break;
23890242f74dSAlex Deucher default:
23900242f74dSAlex Deucher DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
23910242f74dSAlex Deucher prim_walk);
23920242f74dSAlex Deucher return -EINVAL;
23930242f74dSAlex Deucher }
23940242f74dSAlex Deucher
23950242f74dSAlex Deucher if (track->tex_dirty) {
23960242f74dSAlex Deucher track->tex_dirty = false;
23970242f74dSAlex Deucher return r100_cs_track_texture_check(rdev, track);
23980242f74dSAlex Deucher }
23990242f74dSAlex Deucher return 0;
24000242f74dSAlex Deucher }
24010242f74dSAlex Deucher
r100_cs_track_clear(struct radeon_device * rdev,struct r100_cs_track * track)24020242f74dSAlex Deucher void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
24030242f74dSAlex Deucher {
24040242f74dSAlex Deucher unsigned i, face;
24050242f74dSAlex Deucher
24060242f74dSAlex Deucher track->cb_dirty = true;
24070242f74dSAlex Deucher track->zb_dirty = true;
24080242f74dSAlex Deucher track->tex_dirty = true;
24090242f74dSAlex Deucher track->aa_dirty = true;
24100242f74dSAlex Deucher
24110242f74dSAlex Deucher if (rdev->family < CHIP_R300) {
24120242f74dSAlex Deucher track->num_cb = 1;
24130242f74dSAlex Deucher if (rdev->family <= CHIP_RS200)
24140242f74dSAlex Deucher track->num_texture = 3;
24150242f74dSAlex Deucher else
24160242f74dSAlex Deucher track->num_texture = 6;
24170242f74dSAlex Deucher track->maxy = 2048;
24187bf2f607Szhengbin track->separate_cube = true;
24190242f74dSAlex Deucher } else {
24200242f74dSAlex Deucher track->num_cb = 4;
24210242f74dSAlex Deucher track->num_texture = 16;
24220242f74dSAlex Deucher track->maxy = 4096;
24237bf2f607Szhengbin track->separate_cube = false;
24240242f74dSAlex Deucher track->aaresolve = false;
24250242f74dSAlex Deucher track->aa.robj = NULL;
24260242f74dSAlex Deucher }
24270242f74dSAlex Deucher
24280242f74dSAlex Deucher for (i = 0; i < track->num_cb; i++) {
24290242f74dSAlex Deucher track->cb[i].robj = NULL;
24300242f74dSAlex Deucher track->cb[i].pitch = 8192;
24310242f74dSAlex Deucher track->cb[i].cpp = 16;
24320242f74dSAlex Deucher track->cb[i].offset = 0;
24330242f74dSAlex Deucher }
24340242f74dSAlex Deucher track->z_enabled = true;
24350242f74dSAlex Deucher track->zb.robj = NULL;
24360242f74dSAlex Deucher track->zb.pitch = 8192;
24370242f74dSAlex Deucher track->zb.cpp = 4;
24380242f74dSAlex Deucher track->zb.offset = 0;
24390242f74dSAlex Deucher track->vtx_size = 0x7F;
24400242f74dSAlex Deucher track->immd_dwords = 0xFFFFFFFFUL;
24410242f74dSAlex Deucher track->num_arrays = 11;
24420242f74dSAlex Deucher track->max_indx = 0x00FFFFFFUL;
24430242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) {
24440242f74dSAlex Deucher track->arrays[i].robj = NULL;
24450242f74dSAlex Deucher track->arrays[i].esize = 0x7F;
24460242f74dSAlex Deucher }
24470242f74dSAlex Deucher for (i = 0; i < track->num_texture; i++) {
24480242f74dSAlex Deucher track->textures[i].compress_format = R100_TRACK_COMP_NONE;
24490242f74dSAlex Deucher track->textures[i].pitch = 16536;
24500242f74dSAlex Deucher track->textures[i].width = 16536;
24510242f74dSAlex Deucher track->textures[i].height = 16536;
24520242f74dSAlex Deucher track->textures[i].width_11 = 1 << 11;
24530242f74dSAlex Deucher track->textures[i].height_11 = 1 << 11;
24540242f74dSAlex Deucher track->textures[i].num_levels = 12;
24550242f74dSAlex Deucher if (rdev->family <= CHIP_RS200) {
24560242f74dSAlex Deucher track->textures[i].tex_coord_type = 0;
24570242f74dSAlex Deucher track->textures[i].txdepth = 0;
24580242f74dSAlex Deucher } else {
24590242f74dSAlex Deucher track->textures[i].txdepth = 16;
24600242f74dSAlex Deucher track->textures[i].tex_coord_type = 1;
24610242f74dSAlex Deucher }
24620242f74dSAlex Deucher track->textures[i].cpp = 64;
24630242f74dSAlex Deucher track->textures[i].robj = NULL;
24640242f74dSAlex Deucher /* CS IB emission code makes sure texture unit are disabled */
24650242f74dSAlex Deucher track->textures[i].enabled = false;
24660242f74dSAlex Deucher track->textures[i].lookup_disable = false;
24670242f74dSAlex Deucher track->textures[i].roundup_w = true;
24680242f74dSAlex Deucher track->textures[i].roundup_h = true;
24690242f74dSAlex Deucher if (track->separate_cube)
24700242f74dSAlex Deucher for (face = 0; face < 5; face++) {
24710242f74dSAlex Deucher track->textures[i].cube_info[face].robj = NULL;
24720242f74dSAlex Deucher track->textures[i].cube_info[face].width = 16536;
24730242f74dSAlex Deucher track->textures[i].cube_info[face].height = 16536;
24740242f74dSAlex Deucher track->textures[i].cube_info[face].offset = 0;
24750242f74dSAlex Deucher }
24760242f74dSAlex Deucher }
24770242f74dSAlex Deucher }
2478771fe6b9SJerome Glisse
2479771fe6b9SJerome Glisse /*
2480771fe6b9SJerome Glisse * Global GPU functions
2481771fe6b9SJerome Glisse */
r100_errata(struct radeon_device * rdev)24821109ca09SLauri Kasanen static void r100_errata(struct radeon_device *rdev)
2483771fe6b9SJerome Glisse {
2484771fe6b9SJerome Glisse rdev->pll_errata = 0;
2485771fe6b9SJerome Glisse
2486771fe6b9SJerome Glisse if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2487771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2488771fe6b9SJerome Glisse }
2489771fe6b9SJerome Glisse
2490771fe6b9SJerome Glisse if (rdev->family == CHIP_RV100 ||
2491771fe6b9SJerome Glisse rdev->family == CHIP_RS100 ||
2492771fe6b9SJerome Glisse rdev->family == CHIP_RS200) {
2493771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2494771fe6b9SJerome Glisse }
2495771fe6b9SJerome Glisse }
2496771fe6b9SJerome Glisse
r100_rbbm_fifo_wait_for_entry(struct radeon_device * rdev,unsigned n)24971109ca09SLauri Kasanen static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2498771fe6b9SJerome Glisse {
2499771fe6b9SJerome Glisse unsigned i;
2500771fe6b9SJerome Glisse uint32_t tmp;
2501771fe6b9SJerome Glisse
2502771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
2503771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2504771fe6b9SJerome Glisse if (tmp >= n) {
2505771fe6b9SJerome Glisse return 0;
2506771fe6b9SJerome Glisse }
25070e1a351dSSam Ravnborg udelay(1);
2508771fe6b9SJerome Glisse }
2509771fe6b9SJerome Glisse return -1;
2510771fe6b9SJerome Glisse }
2511771fe6b9SJerome Glisse
r100_gui_wait_for_idle(struct radeon_device * rdev)2512771fe6b9SJerome Glisse int r100_gui_wait_for_idle(struct radeon_device *rdev)
2513771fe6b9SJerome Glisse {
2514771fe6b9SJerome Glisse unsigned i;
2515771fe6b9SJerome Glisse uint32_t tmp;
2516771fe6b9SJerome Glisse
2517771fe6b9SJerome Glisse if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
25187ca85295SJoe Perches pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2519771fe6b9SJerome Glisse }
2520771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
2521771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS);
25224612dc97SAlex Deucher if (!(tmp & RADEON_RBBM_ACTIVE)) {
2523771fe6b9SJerome Glisse return 0;
2524771fe6b9SJerome Glisse }
25250e1a351dSSam Ravnborg udelay(1);
2526771fe6b9SJerome Glisse }
2527771fe6b9SJerome Glisse return -1;
2528771fe6b9SJerome Glisse }
2529771fe6b9SJerome Glisse
r100_mc_wait_for_idle(struct radeon_device * rdev)2530771fe6b9SJerome Glisse int r100_mc_wait_for_idle(struct radeon_device *rdev)
2531771fe6b9SJerome Glisse {
2532771fe6b9SJerome Glisse unsigned i;
2533771fe6b9SJerome Glisse uint32_t tmp;
2534771fe6b9SJerome Glisse
2535771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
2536771fe6b9SJerome Glisse /* read MC_STATUS */
25374612dc97SAlex Deucher tmp = RREG32(RADEON_MC_STATUS);
25384612dc97SAlex Deucher if (tmp & RADEON_MC_IDLE) {
2539771fe6b9SJerome Glisse return 0;
2540771fe6b9SJerome Glisse }
25410e1a351dSSam Ravnborg udelay(1);
2542771fe6b9SJerome Glisse }
2543771fe6b9SJerome Glisse return -1;
2544771fe6b9SJerome Glisse }
2545771fe6b9SJerome Glisse
r100_gpu_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)2546e32eb50dSChristian König bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2547771fe6b9SJerome Glisse {
2548225758d8SJerome Glisse u32 rbbm_status;
2549771fe6b9SJerome Glisse
2550225758d8SJerome Glisse rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2551225758d8SJerome Glisse if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2552ff212f25SChristian König radeon_ring_lockup_update(rdev, ring);
2553225758d8SJerome Glisse return false;
2554225758d8SJerome Glisse }
2555069211e5SChristian König return radeon_ring_test_lockup(rdev, ring);
2556225758d8SJerome Glisse }
2557225758d8SJerome Glisse
255874da01dcSAlex Deucher /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
r100_enable_bm(struct radeon_device * rdev)255974da01dcSAlex Deucher void r100_enable_bm(struct radeon_device *rdev)
256074da01dcSAlex Deucher {
256174da01dcSAlex Deucher uint32_t tmp;
256274da01dcSAlex Deucher /* Enable bus mastering */
256374da01dcSAlex Deucher tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
256474da01dcSAlex Deucher WREG32(RADEON_BUS_CNTL, tmp);
256574da01dcSAlex Deucher }
256674da01dcSAlex Deucher
r100_bm_disable(struct radeon_device * rdev)256790aca4d2SJerome Glisse void r100_bm_disable(struct radeon_device *rdev)
256890aca4d2SJerome Glisse {
256990aca4d2SJerome Glisse u32 tmp;
257090aca4d2SJerome Glisse
257190aca4d2SJerome Glisse /* disable bus mastering */
257290aca4d2SJerome Glisse tmp = RREG32(R_000030_BUS_CNTL);
257390aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2574771fe6b9SJerome Glisse mdelay(1);
257590aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
257690aca4d2SJerome Glisse mdelay(1);
257790aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
257890aca4d2SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL);
257990aca4d2SJerome Glisse mdelay(1);
2580642ce525SMichel Dänzer pci_clear_master(rdev->pdev);
258190aca4d2SJerome Glisse mdelay(1);
258290aca4d2SJerome Glisse }
258390aca4d2SJerome Glisse
r100_asic_reset(struct radeon_device * rdev,bool hard)258471fe2899SJérome Glisse int r100_asic_reset(struct radeon_device *rdev, bool hard)
2585771fe6b9SJerome Glisse {
258690aca4d2SJerome Glisse struct r100_mc_save save;
258790aca4d2SJerome Glisse u32 status, tmp;
258825b2ec5bSAlex Deucher int ret = 0;
2589771fe6b9SJerome Glisse
259090aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS);
259190aca4d2SJerome Glisse if (!G_000E40_GUI_ACTIVE(status)) {
2592771fe6b9SJerome Glisse return 0;
2593771fe6b9SJerome Glisse }
259425b2ec5bSAlex Deucher r100_mc_stop(rdev, &save);
259590aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS);
259690aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
259790aca4d2SJerome Glisse /* stop CP */
259890aca4d2SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0);
259990aca4d2SJerome Glisse tmp = RREG32(RADEON_CP_RB_CNTL);
260090aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
260190aca4d2SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0);
260290aca4d2SJerome Glisse WREG32(RADEON_CP_RB_WPTR, 0);
260390aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp);
260490aca4d2SJerome Glisse /* save PCI state */
260590aca4d2SJerome Glisse pci_save_state(rdev->pdev);
260690aca4d2SJerome Glisse /* disable bus mastering */
260790aca4d2SJerome Glisse r100_bm_disable(rdev);
260890aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
260990aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RE(1) |
261090aca4d2SJerome Glisse S_0000F0_SOFT_RESET_PP(1) |
261190aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RB(1));
261290aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET);
261390aca4d2SJerome Glisse mdelay(500);
261490aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
261590aca4d2SJerome Glisse mdelay(1);
261690aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS);
261790aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2618771fe6b9SJerome Glisse /* reset CP */
261990aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
262090aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET);
262190aca4d2SJerome Glisse mdelay(500);
262290aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
262390aca4d2SJerome Glisse mdelay(1);
262490aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS);
262590aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
262690aca4d2SJerome Glisse /* restore PCI & busmastering */
262790aca4d2SJerome Glisse pci_restore_state(rdev->pdev);
262890aca4d2SJerome Glisse r100_enable_bm(rdev);
2629771fe6b9SJerome Glisse /* Check if GPU is idle */
263090aca4d2SJerome Glisse if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
263190aca4d2SJerome Glisse G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
263290aca4d2SJerome Glisse dev_err(rdev->dev, "failed to reset GPU\n");
263325b2ec5bSAlex Deucher ret = -1;
263425b2ec5bSAlex Deucher } else
263590aca4d2SJerome Glisse dev_info(rdev->dev, "GPU reset succeed\n");
263625b2ec5bSAlex Deucher r100_mc_resume(rdev, &save);
263725b2ec5bSAlex Deucher return ret;
2638771fe6b9SJerome Glisse }
2639771fe6b9SJerome Glisse
r100_set_common_regs(struct radeon_device * rdev)264092cde00cSAlex Deucher void r100_set_common_regs(struct radeon_device *rdev)
264192cde00cSAlex Deucher {
26422739d49cSAlex Deucher bool force_dac2 = false;
2643d668046cSDave Airlie u32 tmp;
26442739d49cSAlex Deucher
264592cde00cSAlex Deucher /* set these so they don't interfere with anything */
264692cde00cSAlex Deucher WREG32(RADEON_OV0_SCALE_CNTL, 0);
264792cde00cSAlex Deucher WREG32(RADEON_SUBPIC_CNTL, 0);
264892cde00cSAlex Deucher WREG32(RADEON_VIPH_CONTROL, 0);
264992cde00cSAlex Deucher WREG32(RADEON_I2C_CNTL_1, 0);
265092cde00cSAlex Deucher WREG32(RADEON_DVI_I2C_CNTL_1, 0);
265192cde00cSAlex Deucher WREG32(RADEON_CAP0_TRIG_CNTL, 0);
265292cde00cSAlex Deucher WREG32(RADEON_CAP1_TRIG_CNTL, 0);
26532739d49cSAlex Deucher
26542739d49cSAlex Deucher /* always set up dac2 on rn50 and some rv100 as lots
26552739d49cSAlex Deucher * of servers seem to wire it up to a VGA port but
26562739d49cSAlex Deucher * don't report it in the bios connector
26572739d49cSAlex Deucher * table.
26582739d49cSAlex Deucher */
2659d86a4126SThomas Zimmermann switch (rdev->pdev->device) {
26602739d49cSAlex Deucher /* RN50 */
26612739d49cSAlex Deucher case 0x515e:
26622739d49cSAlex Deucher case 0x5969:
26632739d49cSAlex Deucher force_dac2 = true;
26642739d49cSAlex Deucher break;
26652739d49cSAlex Deucher /* RV100*/
26662739d49cSAlex Deucher case 0x5159:
26672739d49cSAlex Deucher case 0x515a:
26682739d49cSAlex Deucher /* DELL triple head servers */
2669d86a4126SThomas Zimmermann if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2670d86a4126SThomas Zimmermann ((rdev->pdev->subsystem_device == 0x016c) ||
2671d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016d) ||
2672d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016e) ||
2673d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016f) ||
2674d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0170) ||
2675d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017d) ||
2676d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017e) ||
2677d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0183) ||
2678d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x018a) ||
2679d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x019a)))
26802739d49cSAlex Deucher force_dac2 = true;
26812739d49cSAlex Deucher break;
26822739d49cSAlex Deucher }
26832739d49cSAlex Deucher
26842739d49cSAlex Deucher if (force_dac2) {
26852739d49cSAlex Deucher u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
26862739d49cSAlex Deucher u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
26872739d49cSAlex Deucher u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
26882739d49cSAlex Deucher
26892739d49cSAlex Deucher /* For CRT on DAC2, don't turn it on if BIOS didn't
26902739d49cSAlex Deucher enable it, even it's detected.
26912739d49cSAlex Deucher */
26922739d49cSAlex Deucher
26932739d49cSAlex Deucher /* force it to crtc0 */
26942739d49cSAlex Deucher dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
26952739d49cSAlex Deucher dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
26962739d49cSAlex Deucher disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
26972739d49cSAlex Deucher
26982739d49cSAlex Deucher /* set up the TV DAC */
26992739d49cSAlex Deucher tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
27002739d49cSAlex Deucher RADEON_TV_DAC_STD_MASK |
27012739d49cSAlex Deucher RADEON_TV_DAC_RDACPD |
27022739d49cSAlex Deucher RADEON_TV_DAC_GDACPD |
27032739d49cSAlex Deucher RADEON_TV_DAC_BDACPD |
27042739d49cSAlex Deucher RADEON_TV_DAC_BGADJ_MASK |
27052739d49cSAlex Deucher RADEON_TV_DAC_DACADJ_MASK);
27062739d49cSAlex Deucher tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
27072739d49cSAlex Deucher RADEON_TV_DAC_NHOLD |
27082739d49cSAlex Deucher RADEON_TV_DAC_STD_PS2 |
27092739d49cSAlex Deucher (0x58 << 16));
27102739d49cSAlex Deucher
27112739d49cSAlex Deucher WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
27122739d49cSAlex Deucher WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
27132739d49cSAlex Deucher WREG32(RADEON_DAC_CNTL2, dac2_cntl);
27142739d49cSAlex Deucher }
2715d668046cSDave Airlie
2716d668046cSDave Airlie /* switch PM block to ACPI mode */
2717d668046cSDave Airlie tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2718d668046cSDave Airlie tmp &= ~RADEON_PM_MODE_SEL;
2719d668046cSDave Airlie WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2720d668046cSDave Airlie
272192cde00cSAlex Deucher }
2722771fe6b9SJerome Glisse
2723771fe6b9SJerome Glisse /*
2724771fe6b9SJerome Glisse * VRAM info
2725771fe6b9SJerome Glisse */
r100_vram_get_type(struct radeon_device * rdev)2726771fe6b9SJerome Glisse static void r100_vram_get_type(struct radeon_device *rdev)
2727771fe6b9SJerome Glisse {
2728771fe6b9SJerome Glisse uint32_t tmp;
2729771fe6b9SJerome Glisse
2730771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = false;
2731771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP)
2732771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true;
2733771fe6b9SJerome Glisse else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2734771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true;
2735771fe6b9SJerome Glisse if ((rdev->family == CHIP_RV100) ||
2736771fe6b9SJerome Glisse (rdev->family == CHIP_RS100) ||
2737771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) {
2738771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL);
2739771fe6b9SJerome Glisse if (tmp & RV100_HALF_MODE) {
2740771fe6b9SJerome Glisse rdev->mc.vram_width = 32;
2741771fe6b9SJerome Glisse } else {
2742771fe6b9SJerome Glisse rdev->mc.vram_width = 64;
2743771fe6b9SJerome Glisse }
2744771fe6b9SJerome Glisse if (rdev->flags & RADEON_SINGLE_CRTC) {
2745771fe6b9SJerome Glisse rdev->mc.vram_width /= 4;
2746771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true;
2747771fe6b9SJerome Glisse }
2748771fe6b9SJerome Glisse } else if (rdev->family <= CHIP_RV280) {
2749771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL);
2750771fe6b9SJerome Glisse if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2751771fe6b9SJerome Glisse rdev->mc.vram_width = 128;
2752771fe6b9SJerome Glisse } else {
2753771fe6b9SJerome Glisse rdev->mc.vram_width = 64;
2754771fe6b9SJerome Glisse }
2755771fe6b9SJerome Glisse } else {
2756771fe6b9SJerome Glisse /* newer IGPs */
2757771fe6b9SJerome Glisse rdev->mc.vram_width = 128;
2758771fe6b9SJerome Glisse }
2759771fe6b9SJerome Glisse }
2760771fe6b9SJerome Glisse
r100_get_accessible_vram(struct radeon_device * rdev)27612a0f8918SDave Airlie static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2762771fe6b9SJerome Glisse {
27632a0f8918SDave Airlie u32 aper_size;
27642a0f8918SDave Airlie u8 byte;
27652a0f8918SDave Airlie
27662a0f8918SDave Airlie aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
27672a0f8918SDave Airlie
27682a0f8918SDave Airlie /* Set HDP_APER_CNTL only on cards that are known not to be broken,
27692a0f8918SDave Airlie * that is has the 2nd generation multifunction PCI interface
27702a0f8918SDave Airlie */
27712a0f8918SDave Airlie if (rdev->family == CHIP_RV280 ||
27722a0f8918SDave Airlie rdev->family >= CHIP_RV350) {
27732a0f8918SDave Airlie WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
27742a0f8918SDave Airlie ~RADEON_HDP_APER_CNTL);
27752a0f8918SDave Airlie DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
27762a0f8918SDave Airlie return aper_size * 2;
27772a0f8918SDave Airlie }
27782a0f8918SDave Airlie
27792a0f8918SDave Airlie /* Older cards have all sorts of funny issues to deal with. First
27802a0f8918SDave Airlie * check if it's a multifunction card by reading the PCI config
27812a0f8918SDave Airlie * header type... Limit those to one aperture size
27822a0f8918SDave Airlie */
27832a0f8918SDave Airlie pci_read_config_byte(rdev->pdev, 0xe, &byte);
27842a0f8918SDave Airlie if (byte & 0x80) {
27852a0f8918SDave Airlie DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
27862a0f8918SDave Airlie DRM_INFO("Limiting VRAM to one aperture\n");
27872a0f8918SDave Airlie return aper_size;
27882a0f8918SDave Airlie }
27892a0f8918SDave Airlie
27902a0f8918SDave Airlie /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
27912a0f8918SDave Airlie * have set it up. We don't write this as it's broken on some ASICs but
27922a0f8918SDave Airlie * we expect the BIOS to have done the right thing (might be too optimistic...)
27932a0f8918SDave Airlie */
27942a0f8918SDave Airlie if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
27952a0f8918SDave Airlie return aper_size * 2;
27962a0f8918SDave Airlie return aper_size;
27972a0f8918SDave Airlie }
27982a0f8918SDave Airlie
r100_vram_init_sizes(struct radeon_device * rdev)27992a0f8918SDave Airlie void r100_vram_init_sizes(struct radeon_device *rdev)
28002a0f8918SDave Airlie {
28012a0f8918SDave Airlie u64 config_aper_size;
28022a0f8918SDave Airlie
2803d594e46aSJerome Glisse /* work out accessible VRAM */
280401d73a69SJordan Crouse rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
280501d73a69SJordan Crouse rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
280651e5fcd3SJerome Glisse rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
280751e5fcd3SJerome Glisse /* FIXME we don't use the second aperture yet when we could use it */
280851e5fcd3SJerome Glisse if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
280951e5fcd3SJerome Glisse rdev->mc.visible_vram_size = rdev->mc.aper_size;
28102a0f8918SDave Airlie config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2811771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) {
2812771fe6b9SJerome Glisse uint32_t tom;
2813771fe6b9SJerome Glisse /* read NB_TOM to get the amount of ram stolen for the GPU */
2814771fe6b9SJerome Glisse tom = RREG32(RADEON_NB_TOM);
28157a50f01aSDave Airlie rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
28167a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
28177a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2818771fe6b9SJerome Glisse } else {
28197a50f01aSDave Airlie rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2820771fe6b9SJerome Glisse /* Some production boards of m6 will report 0
2821771fe6b9SJerome Glisse * if it's 8 MB
2822771fe6b9SJerome Glisse */
28237a50f01aSDave Airlie if (rdev->mc.real_vram_size == 0) {
28247a50f01aSDave Airlie rdev->mc.real_vram_size = 8192 * 1024;
28257a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2826771fe6b9SJerome Glisse }
28272a0f8918SDave Airlie /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2828d594e46aSJerome Glisse * Novell bug 204882 + along with lots of ubuntu ones
2829d594e46aSJerome Glisse */
2830b7d8cce5SAlex Deucher if (rdev->mc.aper_size > config_aper_size)
2831b7d8cce5SAlex Deucher config_aper_size = rdev->mc.aper_size;
2832b7d8cce5SAlex Deucher
28337a50f01aSDave Airlie if (config_aper_size > rdev->mc.real_vram_size)
28347a50f01aSDave Airlie rdev->mc.mc_vram_size = config_aper_size;
28357a50f01aSDave Airlie else
28367a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2837771fe6b9SJerome Glisse }
2838d594e46aSJerome Glisse }
28392a0f8918SDave Airlie
r100_vga_set_state(struct radeon_device * rdev,bool state)284028d52043SDave Airlie void r100_vga_set_state(struct radeon_device *rdev, bool state)
284128d52043SDave Airlie {
284228d52043SDave Airlie uint32_t temp;
284328d52043SDave Airlie
284428d52043SDave Airlie temp = RREG32(RADEON_CONFIG_CNTL);
2845fbd62354SWambui Karuga if (!state) {
2846d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_RAM_EN;
2847d75ee3beSAlex Deucher temp |= RADEON_CFG_VGA_IO_DIS;
284828d52043SDave Airlie } else {
2849d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_IO_DIS;
285028d52043SDave Airlie }
285128d52043SDave Airlie WREG32(RADEON_CONFIG_CNTL, temp);
285228d52043SDave Airlie }
285328d52043SDave Airlie
r100_mc_init(struct radeon_device * rdev)28541109ca09SLauri Kasanen static void r100_mc_init(struct radeon_device *rdev)
28552a0f8918SDave Airlie {
2856d594e46aSJerome Glisse u64 base;
28572a0f8918SDave Airlie
2858d594e46aSJerome Glisse r100_vram_get_type(rdev);
28592a0f8918SDave Airlie r100_vram_init_sizes(rdev);
2860d594e46aSJerome Glisse base = rdev->mc.aper_base;
2861d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_IGP)
2862d594e46aSJerome Glisse base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2863d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, base);
28648d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0;
2865d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP))
2866d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc);
2867f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev);
2868771fe6b9SJerome Glisse }
2869771fe6b9SJerome Glisse
2870771fe6b9SJerome Glisse
2871771fe6b9SJerome Glisse /*
2872771fe6b9SJerome Glisse * Indirect registers accessor
2873771fe6b9SJerome Glisse */
r100_pll_errata_after_index(struct radeon_device * rdev)2874771fe6b9SJerome Glisse void r100_pll_errata_after_index(struct radeon_device *rdev)
2875771fe6b9SJerome Glisse {
28764ce9198eSAlex Deucher if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2877771fe6b9SJerome Glisse (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2878771fe6b9SJerome Glisse (void)RREG32(RADEON_CRTC_GEN_CNTL);
2879771fe6b9SJerome Glisse }
28804ce9198eSAlex Deucher }
2881771fe6b9SJerome Glisse
r100_pll_errata_after_data(struct radeon_device * rdev)2882771fe6b9SJerome Glisse static void r100_pll_errata_after_data(struct radeon_device *rdev)
2883771fe6b9SJerome Glisse {
2884771fe6b9SJerome Glisse /* This workarounds is necessary on RV100, RS100 and RS200 chips
2885771fe6b9SJerome Glisse * or the chip could hang on a subsequent access
2886771fe6b9SJerome Glisse */
2887771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
28884de833c3SArnd Bergmann mdelay(5);
2889771fe6b9SJerome Glisse }
2890771fe6b9SJerome Glisse
2891771fe6b9SJerome Glisse /* This function is required to workaround a hardware bug in some (all?)
2892771fe6b9SJerome Glisse * revisions of the R300. This workaround should be called after every
2893771fe6b9SJerome Glisse * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2894771fe6b9SJerome Glisse * may not be correct.
2895771fe6b9SJerome Glisse */
2896771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2897771fe6b9SJerome Glisse uint32_t save, tmp;
2898771fe6b9SJerome Glisse
2899771fe6b9SJerome Glisse save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2900771fe6b9SJerome Glisse tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2901771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2902771fe6b9SJerome Glisse tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2903771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2904771fe6b9SJerome Glisse }
2905771fe6b9SJerome Glisse }
2906771fe6b9SJerome Glisse
r100_pll_rreg(struct radeon_device * rdev,uint32_t reg)2907771fe6b9SJerome Glisse uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2908771fe6b9SJerome Glisse {
29090a5b7b0bSAlex Deucher unsigned long flags;
2910771fe6b9SJerome Glisse uint32_t data;
2911771fe6b9SJerome Glisse
29120a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2913771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2914771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev);
2915771fe6b9SJerome Glisse data = RREG32(RADEON_CLOCK_CNTL_DATA);
2916771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev);
29170a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2918771fe6b9SJerome Glisse return data;
2919771fe6b9SJerome Glisse }
2920771fe6b9SJerome Glisse
r100_pll_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)2921771fe6b9SJerome Glisse void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2922771fe6b9SJerome Glisse {
29230a5b7b0bSAlex Deucher unsigned long flags;
29240a5b7b0bSAlex Deucher
29250a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2926771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2927771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev);
2928771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_DATA, v);
2929771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev);
29300a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2931771fe6b9SJerome Glisse }
2932771fe6b9SJerome Glisse
r100_set_safe_registers(struct radeon_device * rdev)29331109ca09SLauri Kasanen static void r100_set_safe_registers(struct radeon_device *rdev)
2934068a117cSJerome Glisse {
2935551ebd83SDave Airlie if (ASIC_IS_RN50(rdev)) {
2936551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2937551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2938551ebd83SDave Airlie } else if (rdev->family < CHIP_R200) {
2939551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2940551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2941551ebd83SDave Airlie } else {
2942d4550907SJerome Glisse r200_set_safe_registers(rdev);
2943551ebd83SDave Airlie }
2944068a117cSJerome Glisse }
2945068a117cSJerome Glisse
2946771fe6b9SJerome Glisse /*
2947771fe6b9SJerome Glisse * Debugfs info
2948771fe6b9SJerome Glisse */
2949771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS)
r100_debugfs_rbbm_info_show(struct seq_file * m,void * unused)29505b54d679SNirmoy Das static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2951771fe6b9SJerome Glisse {
29526091ede9SSu Hui struct radeon_device *rdev = m->private;
2953771fe6b9SJerome Glisse uint32_t reg, value;
2954771fe6b9SJerome Glisse unsigned i;
2955771fe6b9SJerome Glisse
2956771fe6b9SJerome Glisse seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2957771fe6b9SJerome Glisse seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2958771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2959771fe6b9SJerome Glisse for (i = 0; i < 64; i++) {
2960771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2961771fe6b9SJerome Glisse reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2962771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2963771fe6b9SJerome Glisse value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2964771fe6b9SJerome Glisse seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2965771fe6b9SJerome Glisse }
2966771fe6b9SJerome Glisse return 0;
2967771fe6b9SJerome Glisse }
2968771fe6b9SJerome Glisse
r100_debugfs_cp_ring_info_show(struct seq_file * m,void * unused)29695b54d679SNirmoy Das static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2970771fe6b9SJerome Glisse {
29716091ede9SSu Hui struct radeon_device *rdev = m->private;
2972e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2973771fe6b9SJerome Glisse uint32_t rdp, wdp;
2974771fe6b9SJerome Glisse unsigned count, i, j;
2975771fe6b9SJerome Glisse
2976e32eb50dSChristian König radeon_ring_free_size(rdev, ring);
2977771fe6b9SJerome Glisse rdp = RREG32(RADEON_CP_RB_RPTR);
2978771fe6b9SJerome Glisse wdp = RREG32(RADEON_CP_RB_WPTR);
2979e32eb50dSChristian König count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2980771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2981771fe6b9SJerome Glisse seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2982771fe6b9SJerome Glisse seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2983e32eb50dSChristian König seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2984771fe6b9SJerome Glisse seq_printf(m, "%u dwords in ring\n", count);
29850eb3448aSAlex Ivanov if (ring->ready) {
2986771fe6b9SJerome Glisse for (j = 0; j <= count; j++) {
2987e32eb50dSChristian König i = (rdp + j) & ring->ptr_mask;
2988e32eb50dSChristian König seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2989771fe6b9SJerome Glisse }
29900eb3448aSAlex Ivanov }
2991771fe6b9SJerome Glisse return 0;
2992771fe6b9SJerome Glisse }
2993771fe6b9SJerome Glisse
2994771fe6b9SJerome Glisse
r100_debugfs_cp_csq_fifo_show(struct seq_file * m,void * unused)29955b54d679SNirmoy Das static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2996771fe6b9SJerome Glisse {
29976091ede9SSu Hui struct radeon_device *rdev = m->private;
2998771fe6b9SJerome Glisse uint32_t csq_stat, csq2_stat, tmp;
2999771fe6b9SJerome Glisse unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3000771fe6b9SJerome Glisse unsigned i;
3001771fe6b9SJerome Glisse
3002771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3003771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3004771fe6b9SJerome Glisse csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3005771fe6b9SJerome Glisse csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3006771fe6b9SJerome Glisse r_rptr = (csq_stat >> 0) & 0x3ff;
3007771fe6b9SJerome Glisse r_wptr = (csq_stat >> 10) & 0x3ff;
3008771fe6b9SJerome Glisse ib1_rptr = (csq_stat >> 20) & 0x3ff;
3009771fe6b9SJerome Glisse ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3010771fe6b9SJerome Glisse ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3011771fe6b9SJerome Glisse ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3012771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3013771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3014771fe6b9SJerome Glisse seq_printf(m, "Ring rptr %u\n", r_rptr);
3015771fe6b9SJerome Glisse seq_printf(m, "Ring wptr %u\n", r_wptr);
3016771fe6b9SJerome Glisse seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3017771fe6b9SJerome Glisse seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3018771fe6b9SJerome Glisse seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3019771fe6b9SJerome Glisse seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3020771fe6b9SJerome Glisse /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3021771fe6b9SJerome Glisse * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3022771fe6b9SJerome Glisse seq_printf(m, "Ring fifo:\n");
3023771fe6b9SJerome Glisse for (i = 0; i < 256; i++) {
3024771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3025771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA);
3026771fe6b9SJerome Glisse seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3027771fe6b9SJerome Glisse }
3028771fe6b9SJerome Glisse seq_printf(m, "Indirect1 fifo:\n");
3029771fe6b9SJerome Glisse for (i = 256; i <= 512; i++) {
3030771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3031771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA);
3032771fe6b9SJerome Glisse seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3033771fe6b9SJerome Glisse }
3034771fe6b9SJerome Glisse seq_printf(m, "Indirect2 fifo:\n");
3035771fe6b9SJerome Glisse for (i = 640; i < ib1_wptr; i++) {
3036771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3037771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA);
3038771fe6b9SJerome Glisse seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3039771fe6b9SJerome Glisse }
3040771fe6b9SJerome Glisse return 0;
3041771fe6b9SJerome Glisse }
3042771fe6b9SJerome Glisse
r100_debugfs_mc_info_show(struct seq_file * m,void * unused)30435b54d679SNirmoy Das static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3044771fe6b9SJerome Glisse {
30456091ede9SSu Hui struct radeon_device *rdev = m->private;
3046771fe6b9SJerome Glisse uint32_t tmp;
3047771fe6b9SJerome Glisse
3048771fe6b9SJerome Glisse tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3049771fe6b9SJerome Glisse seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3050771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_FB_LOCATION);
3051771fe6b9SJerome Glisse seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3052771fe6b9SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL);
3053771fe6b9SJerome Glisse seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3054771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_AGP_LOCATION);
3055771fe6b9SJerome Glisse seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3056771fe6b9SJerome Glisse tmp = RREG32(RADEON_AGP_BASE);
3057771fe6b9SJerome Glisse seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3058771fe6b9SJerome Glisse tmp = RREG32(RADEON_HOST_PATH_CNTL);
3059771fe6b9SJerome Glisse seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3060771fe6b9SJerome Glisse tmp = RREG32(0x01D0);
3061771fe6b9SJerome Glisse seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3062771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_LO_ADDR);
3063771fe6b9SJerome Glisse seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3064771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_HI_ADDR);
3065771fe6b9SJerome Glisse seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3066771fe6b9SJerome Glisse tmp = RREG32(0x01E4);
3067771fe6b9SJerome Glisse seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3068771fe6b9SJerome Glisse return 0;
3069771fe6b9SJerome Glisse }
3070771fe6b9SJerome Glisse
30715b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
30725b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
30735b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
30745b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
3075771fe6b9SJerome Glisse
3076771fe6b9SJerome Glisse #endif
3077771fe6b9SJerome Glisse
r100_debugfs_rbbm_init(struct radeon_device * rdev)30785b54d679SNirmoy Das void r100_debugfs_rbbm_init(struct radeon_device *rdev)
3079771fe6b9SJerome Glisse {
3080771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS)
3081*5e3a0f77SWu Hoi Pok struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
30825b54d679SNirmoy Das
30835b54d679SNirmoy Das debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
30845b54d679SNirmoy Das &r100_debugfs_rbbm_info_fops);
3085771fe6b9SJerome Glisse #endif
3086771fe6b9SJerome Glisse }
3087771fe6b9SJerome Glisse
r100_debugfs_cp_init(struct radeon_device * rdev)30885b54d679SNirmoy Das void r100_debugfs_cp_init(struct radeon_device *rdev)
3089771fe6b9SJerome Glisse {
3090771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS)
3091*5e3a0f77SWu Hoi Pok struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
30925b54d679SNirmoy Das
30935b54d679SNirmoy Das debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
30945b54d679SNirmoy Das &r100_debugfs_cp_ring_info_fops);
30955b54d679SNirmoy Das debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
30965b54d679SNirmoy Das &r100_debugfs_cp_csq_fifo_fops);
3097771fe6b9SJerome Glisse #endif
3098771fe6b9SJerome Glisse }
3099771fe6b9SJerome Glisse
r100_debugfs_mc_info_init(struct radeon_device * rdev)31005b54d679SNirmoy Das void r100_debugfs_mc_info_init(struct radeon_device *rdev)
3101771fe6b9SJerome Glisse {
3102771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS)
3103*5e3a0f77SWu Hoi Pok struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
31045b54d679SNirmoy Das
31055b54d679SNirmoy Das debugfs_create_file("r100_mc_info", 0444, root, rdev,
31065b54d679SNirmoy Das &r100_debugfs_mc_info_fops);
3107771fe6b9SJerome Glisse #endif
3108771fe6b9SJerome Glisse }
3109e024e110SDave Airlie
r100_set_surface_reg(struct radeon_device * rdev,int reg,uint32_t tiling_flags,uint32_t pitch,uint32_t offset,uint32_t obj_size)3110e024e110SDave Airlie int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3111e024e110SDave Airlie uint32_t tiling_flags, uint32_t pitch,
3112e024e110SDave Airlie uint32_t offset, uint32_t obj_size)
3113e024e110SDave Airlie {
3114e024e110SDave Airlie int surf_index = reg * 16;
3115e024e110SDave Airlie int flags = 0;
3116e024e110SDave Airlie
3117e024e110SDave Airlie if (rdev->family <= CHIP_RS200) {
3118e024e110SDave Airlie if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3119e024e110SDave Airlie == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3120e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_BOTH;
3121e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO)
3122e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_MACRO;
312367d5ced5SAlex Deucher /* setting pitch to 0 disables tiling */
312467d5ced5SAlex Deucher if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
312567d5ced5SAlex Deucher == 0)
312667d5ced5SAlex Deucher pitch = 0;
3127e024e110SDave Airlie } else if (rdev->family <= CHIP_RV280) {
3128e024e110SDave Airlie if (tiling_flags & (RADEON_TILING_MACRO))
3129e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MACRO;
3130e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO)
3131e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MICRO;
3132e024e110SDave Airlie } else {
3133e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO)
3134e024e110SDave Airlie flags |= R300_SURF_TILE_MACRO;
3135e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO)
3136e024e110SDave Airlie flags |= R300_SURF_TILE_MICRO;
3137e024e110SDave Airlie }
3138e024e110SDave Airlie
3139c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3140c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3141c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3142c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3143c88f9f0cSMichel Dänzer
3144f5c5f040SDave Airlie /* r100/r200 divide by 16 */
3145f5c5f040SDave Airlie if (rdev->family < CHIP_R300)
3146f5c5f040SDave Airlie flags |= pitch / 16;
3147f5c5f040SDave Airlie else
3148f5c5f040SDave Airlie flags |= pitch / 8;
3149f5c5f040SDave Airlie
3150f5c5f040SDave Airlie
3151d9fdaafbSDave Airlie DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3152e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3153e024e110SDave Airlie WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3154e024e110SDave Airlie WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3155e024e110SDave Airlie return 0;
3156e024e110SDave Airlie }
3157e024e110SDave Airlie
r100_clear_surface_reg(struct radeon_device * rdev,int reg)3158e024e110SDave Airlie void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3159e024e110SDave Airlie {
3160e024e110SDave Airlie int surf_index = reg * 16;
3161e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3162e024e110SDave Airlie }
3163c93bb85bSJerome Glisse
r100_bandwidth_update(struct radeon_device * rdev)3164c93bb85bSJerome Glisse void r100_bandwidth_update(struct radeon_device *rdev)
3165c93bb85bSJerome Glisse {
3166c93bb85bSJerome Glisse fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3167c93bb85bSJerome Glisse fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
31681ef897e4STim Gardner fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
31691ef897e4STim Gardner fixed20_12 crit_point_ff = {0};
3170c93bb85bSJerome Glisse uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3171c93bb85bSJerome Glisse fixed20_12 memtcas_ff[8] = {
317268adac5eSBen Skeggs dfixed_init(1),
317368adac5eSBen Skeggs dfixed_init(2),
317468adac5eSBen Skeggs dfixed_init(3),
317568adac5eSBen Skeggs dfixed_init(0),
317668adac5eSBen Skeggs dfixed_init_half(1),
317768adac5eSBen Skeggs dfixed_init_half(2),
317868adac5eSBen Skeggs dfixed_init(0),
3179c93bb85bSJerome Glisse };
3180c93bb85bSJerome Glisse fixed20_12 memtcas_rs480_ff[8] = {
318168adac5eSBen Skeggs dfixed_init(0),
318268adac5eSBen Skeggs dfixed_init(1),
318368adac5eSBen Skeggs dfixed_init(2),
318468adac5eSBen Skeggs dfixed_init(3),
318568adac5eSBen Skeggs dfixed_init(0),
318668adac5eSBen Skeggs dfixed_init_half(1),
318768adac5eSBen Skeggs dfixed_init_half(2),
318868adac5eSBen Skeggs dfixed_init_half(3),
3189c93bb85bSJerome Glisse };
3190c93bb85bSJerome Glisse fixed20_12 memtcas2_ff[8] = {
319168adac5eSBen Skeggs dfixed_init(0),
319268adac5eSBen Skeggs dfixed_init(1),
319368adac5eSBen Skeggs dfixed_init(2),
319468adac5eSBen Skeggs dfixed_init(3),
319568adac5eSBen Skeggs dfixed_init(4),
319668adac5eSBen Skeggs dfixed_init(5),
319768adac5eSBen Skeggs dfixed_init(6),
319868adac5eSBen Skeggs dfixed_init(7),
3199c93bb85bSJerome Glisse };
3200c93bb85bSJerome Glisse fixed20_12 memtrbs[8] = {
320168adac5eSBen Skeggs dfixed_init(1),
320268adac5eSBen Skeggs dfixed_init_half(1),
320368adac5eSBen Skeggs dfixed_init(2),
320468adac5eSBen Skeggs dfixed_init_half(2),
320568adac5eSBen Skeggs dfixed_init(3),
320668adac5eSBen Skeggs dfixed_init_half(3),
320768adac5eSBen Skeggs dfixed_init(4),
320868adac5eSBen Skeggs dfixed_init_half(4)
3209c93bb85bSJerome Glisse };
3210c93bb85bSJerome Glisse fixed20_12 memtrbs_r4xx[8] = {
321168adac5eSBen Skeggs dfixed_init(4),
321268adac5eSBen Skeggs dfixed_init(5),
321368adac5eSBen Skeggs dfixed_init(6),
321468adac5eSBen Skeggs dfixed_init(7),
321568adac5eSBen Skeggs dfixed_init(8),
321668adac5eSBen Skeggs dfixed_init(9),
321768adac5eSBen Skeggs dfixed_init(10),
321868adac5eSBen Skeggs dfixed_init(11)
3219c93bb85bSJerome Glisse };
3220c93bb85bSJerome Glisse fixed20_12 min_mem_eff;
3221c93bb85bSJerome Glisse fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3222c93bb85bSJerome Glisse fixed20_12 cur_latency_mclk, cur_latency_sclk;
32231ef897e4STim Gardner fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3224c93bb85bSJerome Glisse disp_drain_rate2, read_return_rate;
3225c93bb85bSJerome Glisse fixed20_12 time_disp1_drop_priority;
3226c93bb85bSJerome Glisse int c;
3227c93bb85bSJerome Glisse int cur_size = 16; /* in octawords */
3228c93bb85bSJerome Glisse int critical_point = 0, critical_point2;
3229c93bb85bSJerome Glisse /* uint32_t read_return_rate, time_disp1_drop_priority; */
3230c93bb85bSJerome Glisse int stop_req, max_stop_req;
3231c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL;
3232c93bb85bSJerome Glisse struct drm_display_mode *mode2 = NULL;
3233c93bb85bSJerome Glisse uint32_t pixel_bytes1 = 0;
3234c93bb85bSJerome Glisse uint32_t pixel_bytes2 = 0;
3235c93bb85bSJerome Glisse
32365b5561b3SMario Kleiner /* Guess line buffer size to be 8192 pixels */
32375b5561b3SMario Kleiner u32 lb_size = 8192;
32385b5561b3SMario Kleiner
32398efe82caSAlex Deucher if (!rdev->mode_info.mode_config_initialized)
32408efe82caSAlex Deucher return;
32418efe82caSAlex Deucher
3242f46c0120SAlex Deucher radeon_update_display_priority(rdev);
3243f46c0120SAlex Deucher
3244c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) {
3245489f3267SVille Syrjälä const struct drm_framebuffer *fb =
3246489f3267SVille Syrjälä rdev->mode_info.crtcs[0]->base.primary->fb;
3247489f3267SVille Syrjälä
3248c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3249272725c7SVille Syrjälä pixel_bytes1 = fb->format->cpp[0];
3250c93bb85bSJerome Glisse }
3251dfee5614SDave Airlie if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3252c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) {
3253489f3267SVille Syrjälä const struct drm_framebuffer *fb =
3254489f3267SVille Syrjälä rdev->mode_info.crtcs[1]->base.primary->fb;
3255489f3267SVille Syrjälä
3256c93bb85bSJerome Glisse mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3257272725c7SVille Syrjälä pixel_bytes2 = fb->format->cpp[0];
3258c93bb85bSJerome Glisse }
3259dfee5614SDave Airlie }
3260c93bb85bSJerome Glisse
326168adac5eSBen Skeggs min_mem_eff.full = dfixed_const_8(0);
3262c93bb85bSJerome Glisse /* get modes */
3263c93bb85bSJerome Glisse if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3264c93bb85bSJerome Glisse uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3265c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3266c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3267c93bb85bSJerome Glisse /* check crtc enables */
3268c93bb85bSJerome Glisse if (mode2)
3269c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3270c93bb85bSJerome Glisse if (mode1)
3271c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3272c93bb85bSJerome Glisse WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3273c93bb85bSJerome Glisse }
3274c93bb85bSJerome Glisse
3275c93bb85bSJerome Glisse /*
3276c93bb85bSJerome Glisse * determine is there is enough bw for current mode
3277c93bb85bSJerome Glisse */
3278f47299c5SAlex Deucher sclk_ff = rdev->pm.sclk;
3279f47299c5SAlex Deucher mclk_ff = rdev->pm.mclk;
3280c93bb85bSJerome Glisse
3281c93bb85bSJerome Glisse temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
328268adac5eSBen Skeggs temp_ff.full = dfixed_const(temp);
328368adac5eSBen Skeggs mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3284c93bb85bSJerome Glisse
3285c93bb85bSJerome Glisse pix_clk.full = 0;
3286c93bb85bSJerome Glisse pix_clk2.full = 0;
3287c93bb85bSJerome Glisse peak_disp_bw.full = 0;
3288c93bb85bSJerome Glisse if (mode1) {
328968adac5eSBen Skeggs temp_ff.full = dfixed_const(1000);
329068adac5eSBen Skeggs pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
329168adac5eSBen Skeggs pix_clk.full = dfixed_div(pix_clk, temp_ff);
329268adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes1);
329368adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3294c93bb85bSJerome Glisse }
3295c93bb85bSJerome Glisse if (mode2) {
329668adac5eSBen Skeggs temp_ff.full = dfixed_const(1000);
329768adac5eSBen Skeggs pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
329868adac5eSBen Skeggs pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
329968adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes2);
330068adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3301c93bb85bSJerome Glisse }
3302c93bb85bSJerome Glisse
330368adac5eSBen Skeggs mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3304c93bb85bSJerome Glisse if (peak_disp_bw.full >= mem_bw.full) {
3305c93bb85bSJerome Glisse DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3306c93bb85bSJerome Glisse "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3307c93bb85bSJerome Glisse }
3308c93bb85bSJerome Glisse
3309c93bb85bSJerome Glisse /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3310c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_TIMING_CNTL);
3311c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3312c93bb85bSJerome Glisse mem_trcd = ((temp >> 2) & 0x3) + 1;
3313c93bb85bSJerome Glisse mem_trp = ((temp & 0x3)) + 1;
3314c93bb85bSJerome Glisse mem_tras = ((temp & 0x70) >> 4) + 1;
3315c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R300 ||
3316c93bb85bSJerome Glisse rdev->family == CHIP_R350) { /* r300, r350 */
3317c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1;
3318c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1;
3319c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 4;
3320c93bb85bSJerome Glisse } else if (rdev->family == CHIP_RV350 ||
3321211eed65SAlex Deucher rdev->family == CHIP_RV380) {
3322c93bb85bSJerome Glisse /* rv3x0 */
3323c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 3;
3324c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 3;
3325c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 6;
3326c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R420 ||
3327c93bb85bSJerome Glisse rdev->family == CHIP_R423 ||
3328c93bb85bSJerome Glisse rdev->family == CHIP_RV410) {
3329c93bb85bSJerome Glisse /* r4xx */
3330c93bb85bSJerome Glisse mem_trcd = (temp & 0xf) + 3;
3331c93bb85bSJerome Glisse if (mem_trcd > 15)
3332c93bb85bSJerome Glisse mem_trcd = 15;
3333c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0xf) + 3;
3334c93bb85bSJerome Glisse if (mem_trp > 15)
3335c93bb85bSJerome Glisse mem_trp = 15;
3336c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0x1f) + 6;
3337c93bb85bSJerome Glisse if (mem_tras > 31)
3338c93bb85bSJerome Glisse mem_tras = 31;
3339c93bb85bSJerome Glisse } else { /* RV200, R200 */
3340c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1;
3341c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1;
3342c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0xf) + 4;
3343c93bb85bSJerome Glisse }
3344c93bb85bSJerome Glisse /* convert to FF */
334568adac5eSBen Skeggs trcd_ff.full = dfixed_const(mem_trcd);
334668adac5eSBen Skeggs trp_ff.full = dfixed_const(mem_trp);
334768adac5eSBen Skeggs tras_ff.full = dfixed_const(mem_tras);
3348c93bb85bSJerome Glisse
3349c93bb85bSJerome Glisse /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3350c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3351c93bb85bSJerome Glisse data = (temp & (7 << 20)) >> 20;
3352c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3353c93bb85bSJerome Glisse if (rdev->family == CHIP_RS480) /* don't think rs400 */
3354c93bb85bSJerome Glisse tcas_ff = memtcas_rs480_ff[data];
3355c93bb85bSJerome Glisse else
3356c93bb85bSJerome Glisse tcas_ff = memtcas_ff[data];
3357c93bb85bSJerome Glisse } else
3358c93bb85bSJerome Glisse tcas_ff = memtcas2_ff[data];
3359c93bb85bSJerome Glisse
3360c93bb85bSJerome Glisse if (rdev->family == CHIP_RS400 ||
3361c93bb85bSJerome Glisse rdev->family == CHIP_RS480) {
3362c93bb85bSJerome Glisse /* extra cas latency stored in bits 23-25 0-4 clocks */
3363c93bb85bSJerome Glisse data = (temp >> 23) & 0x7;
3364c93bb85bSJerome Glisse if (data < 5)
336568adac5eSBen Skeggs tcas_ff.full += dfixed_const(data);
3366c93bb85bSJerome Glisse }
3367c93bb85bSJerome Glisse
3368c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3369c93bb85bSJerome Glisse /* on the R300, Tcas is included in Trbs.
3370c93bb85bSJerome Glisse */
3371c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_CNTL);
3372c93bb85bSJerome Glisse data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3373c93bb85bSJerome Glisse if (data == 1) {
3374c93bb85bSJerome Glisse if (R300_MEM_USE_CD_CH_ONLY & temp) {
3375c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_INDEX);
3376c93bb85bSJerome Glisse temp &= ~R300_MC_IND_ADDR_MASK;
3377c93bb85bSJerome Glisse temp |= R300_MC_READ_CNTL_CD_mcind;
3378c93bb85bSJerome Glisse WREG32(R300_MC_IND_INDEX, temp);
3379c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_DATA);
3380c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3381c93bb85bSJerome Glisse } else {
3382c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB);
3383c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3384c93bb85bSJerome Glisse }
3385c93bb85bSJerome Glisse } else {
3386c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB);
3387c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3388c93bb85bSJerome Glisse }
3389c93bb85bSJerome Glisse if (rdev->family == CHIP_RV410 ||
3390c93bb85bSJerome Glisse rdev->family == CHIP_R420 ||
3391c93bb85bSJerome Glisse rdev->family == CHIP_R423)
3392c93bb85bSJerome Glisse trbs_ff = memtrbs_r4xx[data];
3393c93bb85bSJerome Glisse else
3394c93bb85bSJerome Glisse trbs_ff = memtrbs[data];
3395c93bb85bSJerome Glisse tcas_ff.full += trbs_ff.full;
3396c93bb85bSJerome Glisse }
3397c93bb85bSJerome Glisse
3398c93bb85bSJerome Glisse sclk_eff_ff.full = sclk_ff.full;
3399c93bb85bSJerome Glisse
3400c93bb85bSJerome Glisse if (rdev->flags & RADEON_IS_AGP) {
3401c93bb85bSJerome Glisse fixed20_12 agpmode_ff;
340268adac5eSBen Skeggs agpmode_ff.full = dfixed_const(radeon_agpmode);
340368adac5eSBen Skeggs temp_ff.full = dfixed_const_666(16);
340468adac5eSBen Skeggs sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3405c93bb85bSJerome Glisse }
3406c93bb85bSJerome Glisse /* TODO PCIE lanes may affect this - agpmode == 16?? */
3407c93bb85bSJerome Glisse
3408c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev)) {
340968adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(250);
3410c93bb85bSJerome Glisse } else {
3411c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) ||
3412c93bb85bSJerome Glisse rdev->flags & RADEON_IS_IGP) {
3413c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr)
341468adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41);
3415c93bb85bSJerome Glisse else
341668adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(33);
3417c93bb85bSJerome Glisse } else {
3418c93bb85bSJerome Glisse if (rdev->mc.vram_width == 128)
341968adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(57);
3420c93bb85bSJerome Glisse else
342168adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41);
3422c93bb85bSJerome Glisse }
3423c93bb85bSJerome Glisse }
3424c93bb85bSJerome Glisse
342568adac5eSBen Skeggs mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3426c93bb85bSJerome Glisse
3427c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) {
3428c93bb85bSJerome Glisse if (rdev->mc.vram_width == 32) {
342968adac5eSBen Skeggs k1.full = dfixed_const(40);
3430c93bb85bSJerome Glisse c = 3;
3431c93bb85bSJerome Glisse } else {
343268adac5eSBen Skeggs k1.full = dfixed_const(20);
3433c93bb85bSJerome Glisse c = 1;
3434c93bb85bSJerome Glisse }
3435c93bb85bSJerome Glisse } else {
343668adac5eSBen Skeggs k1.full = dfixed_const(40);
3437c93bb85bSJerome Glisse c = 3;
3438c93bb85bSJerome Glisse }
3439c93bb85bSJerome Glisse
344068adac5eSBen Skeggs temp_ff.full = dfixed_const(2);
344168adac5eSBen Skeggs mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
344268adac5eSBen Skeggs temp_ff.full = dfixed_const(c);
344368adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
344468adac5eSBen Skeggs temp_ff.full = dfixed_const(4);
344568adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
344668adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3447c93bb85bSJerome Glisse mc_latency_mclk.full += k1.full;
3448c93bb85bSJerome Glisse
344968adac5eSBen Skeggs mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
345068adac5eSBen Skeggs mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3451c93bb85bSJerome Glisse
3452c93bb85bSJerome Glisse /*
3453c93bb85bSJerome Glisse HW cursor time assuming worst case of full size colour cursor.
3454c93bb85bSJerome Glisse */
345568adac5eSBen Skeggs temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3456c93bb85bSJerome Glisse temp_ff.full += trcd_ff.full;
3457c93bb85bSJerome Glisse if (temp_ff.full < tras_ff.full)
3458c93bb85bSJerome Glisse temp_ff.full = tras_ff.full;
345968adac5eSBen Skeggs cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3460c93bb85bSJerome Glisse
346168adac5eSBen Skeggs temp_ff.full = dfixed_const(cur_size);
346268adac5eSBen Skeggs cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3463c93bb85bSJerome Glisse /*
3464c93bb85bSJerome Glisse Find the total latency for the display data.
3465c93bb85bSJerome Glisse */
346668adac5eSBen Skeggs disp_latency_overhead.full = dfixed_const(8);
346768adac5eSBen Skeggs disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3468c93bb85bSJerome Glisse mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3469c93bb85bSJerome Glisse mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3470c93bb85bSJerome Glisse
3471c93bb85bSJerome Glisse if (mc_latency_mclk.full > mc_latency_sclk.full)
3472c93bb85bSJerome Glisse disp_latency.full = mc_latency_mclk.full;
3473c93bb85bSJerome Glisse else
3474c93bb85bSJerome Glisse disp_latency.full = mc_latency_sclk.full;
3475c93bb85bSJerome Glisse
3476c93bb85bSJerome Glisse /* setup Max GRPH_STOP_REQ default value */
3477c93bb85bSJerome Glisse if (ASIC_IS_RV100(rdev))
3478c93bb85bSJerome Glisse max_stop_req = 0x5c;
3479c93bb85bSJerome Glisse else
3480c93bb85bSJerome Glisse max_stop_req = 0x7c;
3481c93bb85bSJerome Glisse
3482c93bb85bSJerome Glisse if (mode1) {
3483c93bb85bSJerome Glisse /* CRTC1
3484c93bb85bSJerome Glisse Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3485c93bb85bSJerome Glisse GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3486c93bb85bSJerome Glisse */
3487c93bb85bSJerome Glisse stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3488c93bb85bSJerome Glisse
3489c93bb85bSJerome Glisse if (stop_req > max_stop_req)
3490c93bb85bSJerome Glisse stop_req = max_stop_req;
3491c93bb85bSJerome Glisse
3492c93bb85bSJerome Glisse /*
3493c93bb85bSJerome Glisse Find the drain rate of the display buffer.
3494c93bb85bSJerome Glisse */
349568adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes1));
349668adac5eSBen Skeggs disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3497c93bb85bSJerome Glisse
3498c93bb85bSJerome Glisse /*
3499c93bb85bSJerome Glisse Find the critical point of the display buffer.
3500c93bb85bSJerome Glisse */
350168adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
350268adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0);
3503c93bb85bSJerome Glisse
350468adac5eSBen Skeggs critical_point = dfixed_trunc(crit_point_ff);
3505c93bb85bSJerome Glisse
3506c93bb85bSJerome Glisse if (rdev->disp_priority == 2) {
3507c93bb85bSJerome Glisse critical_point = 0;
3508c93bb85bSJerome Glisse }
3509c93bb85bSJerome Glisse
3510c93bb85bSJerome Glisse /*
3511c93bb85bSJerome Glisse The critical point should never be above max_stop_req-4. Setting
3512c93bb85bSJerome Glisse GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3513c93bb85bSJerome Glisse */
3514c93bb85bSJerome Glisse if (max_stop_req - critical_point < 4)
3515c93bb85bSJerome Glisse critical_point = 0;
3516c93bb85bSJerome Glisse
3517c93bb85bSJerome Glisse if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3518c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3519c93bb85bSJerome Glisse critical_point = 0x10;
3520c93bb85bSJerome Glisse }
3521c93bb85bSJerome Glisse
3522c93bb85bSJerome Glisse temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3523c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3524c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3525c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_START_REQ_MASK);
3526c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) &&
3527c93bb85bSJerome Glisse (stop_req > 0x15)) {
3528c93bb85bSJerome Glisse stop_req -= 0x10;
3529c93bb85bSJerome Glisse }
3530c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3531c93bb85bSJerome Glisse temp |= RADEON_GRPH_BUFFER_SIZE;
3532c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3533c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF |
3534c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL);
3535c93bb85bSJerome Glisse /*
3536c93bb85bSJerome Glisse Write the result into the register.
3537c93bb85bSJerome Glisse */
3538c93bb85bSJerome Glisse WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3539c93bb85bSJerome Glisse (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3540c93bb85bSJerome Glisse
3541c93bb85bSJerome Glisse #if 0
3542c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) ||
3543c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) {
3544c93bb85bSJerome Glisse /* attempt to program RS400 disp regs correctly ??? */
3545c93bb85bSJerome Glisse temp = RREG32(RS400_DISP1_REG_CNTL);
3546c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3547c93bb85bSJerome Glisse RS400_DISP1_STOP_REQ_LEVEL_MASK);
3548c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3549c93bb85bSJerome Glisse (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3550c93bb85bSJerome Glisse (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3551c93bb85bSJerome Glisse temp = RREG32(RS400_DMIF_MEM_CNTL1);
3552c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3553c93bb85bSJerome Glisse RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3554c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3555c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3556c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3557c93bb85bSJerome Glisse }
3558c93bb85bSJerome Glisse #endif
3559c93bb85bSJerome Glisse
3560d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3561c93bb85bSJerome Glisse /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3562c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3563c93bb85bSJerome Glisse }
3564c93bb85bSJerome Glisse
3565c93bb85bSJerome Glisse if (mode2) {
3566c93bb85bSJerome Glisse u32 grph2_cntl;
3567c93bb85bSJerome Glisse stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3568c93bb85bSJerome Glisse
3569c93bb85bSJerome Glisse if (stop_req > max_stop_req)
3570c93bb85bSJerome Glisse stop_req = max_stop_req;
3571c93bb85bSJerome Glisse
3572c93bb85bSJerome Glisse /*
3573c93bb85bSJerome Glisse Find the drain rate of the display buffer.
3574c93bb85bSJerome Glisse */
357568adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes2));
357668adac5eSBen Skeggs disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3577c93bb85bSJerome Glisse
3578c93bb85bSJerome Glisse grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3579c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3580c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3581c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3582c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) &&
3583c93bb85bSJerome Glisse (stop_req > 0x15)) {
3584c93bb85bSJerome Glisse stop_req -= 0x10;
3585c93bb85bSJerome Glisse }
3586c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3587c93bb85bSJerome Glisse grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3588c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3589c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF |
3590c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL);
3591c93bb85bSJerome Glisse
3592c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS100) ||
3593c93bb85bSJerome Glisse (rdev->family == CHIP_RS200))
3594c93bb85bSJerome Glisse critical_point2 = 0;
3595c93bb85bSJerome Glisse else {
3596c93bb85bSJerome Glisse temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
359768adac5eSBen Skeggs temp_ff.full = dfixed_const(temp);
359868adac5eSBen Skeggs temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3599c93bb85bSJerome Glisse if (sclk_ff.full < temp_ff.full)
3600c93bb85bSJerome Glisse temp_ff.full = sclk_ff.full;
3601c93bb85bSJerome Glisse
3602c93bb85bSJerome Glisse read_return_rate.full = temp_ff.full;
3603c93bb85bSJerome Glisse
3604c93bb85bSJerome Glisse if (mode1) {
3605c93bb85bSJerome Glisse temp_ff.full = read_return_rate.full - disp_drain_rate.full;
360668adac5eSBen Skeggs time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3607c93bb85bSJerome Glisse } else {
3608c93bb85bSJerome Glisse time_disp1_drop_priority.full = 0;
3609c93bb85bSJerome Glisse }
3610c93bb85bSJerome Glisse crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
361168adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
361268adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0);
3613c93bb85bSJerome Glisse
361468adac5eSBen Skeggs critical_point2 = dfixed_trunc(crit_point_ff);
3615c93bb85bSJerome Glisse
3616c93bb85bSJerome Glisse if (rdev->disp_priority == 2) {
3617c93bb85bSJerome Glisse critical_point2 = 0;
3618c93bb85bSJerome Glisse }
3619c93bb85bSJerome Glisse
3620c93bb85bSJerome Glisse if (max_stop_req - critical_point2 < 4)
3621c93bb85bSJerome Glisse critical_point2 = 0;
3622c93bb85bSJerome Glisse
3623c93bb85bSJerome Glisse }
3624c93bb85bSJerome Glisse
3625c93bb85bSJerome Glisse if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3626c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0 */
3627c93bb85bSJerome Glisse critical_point2 = 0x10;
3628c93bb85bSJerome Glisse }
3629c93bb85bSJerome Glisse
3630c93bb85bSJerome Glisse WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3631c93bb85bSJerome Glisse (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3632c93bb85bSJerome Glisse
3633c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) ||
3634c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) {
3635c93bb85bSJerome Glisse #if 0
3636c93bb85bSJerome Glisse /* attempt to program RS400 disp2 regs correctly ??? */
3637c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL1);
3638c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3639c93bb85bSJerome Glisse RS400_DISP2_STOP_REQ_LEVEL_MASK);
3640c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3641c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3642c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3643c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL2);
3644c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3645c93bb85bSJerome Glisse RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3646c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3647c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3648c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3649c93bb85bSJerome Glisse #endif
3650c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3651c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3652c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3653c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3654c93bb85bSJerome Glisse }
3655c93bb85bSJerome Glisse
3656d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3657c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3658c93bb85bSJerome Glisse }
36595b5561b3SMario Kleiner
36605b5561b3SMario Kleiner /* Save number of lines the linebuffer leads before the scanout */
36615b5561b3SMario Kleiner if (mode1)
36625b5561b3SMario Kleiner rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
36635b5561b3SMario Kleiner
36645b5561b3SMario Kleiner if (mode2)
36655b5561b3SMario Kleiner rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3666c93bb85bSJerome Glisse }
3667551ebd83SDave Airlie
r100_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)3668e32eb50dSChristian König int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
36693ce0a23dSJerome Glisse {
36703ce0a23dSJerome Glisse uint32_t scratch;
36713ce0a23dSJerome Glisse uint32_t tmp = 0;
36723ce0a23dSJerome Glisse unsigned i;
36733ce0a23dSJerome Glisse int r;
36743ce0a23dSJerome Glisse
36753ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch);
36763ce0a23dSJerome Glisse if (r) {
36773ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
36783ce0a23dSJerome Glisse return r;
36793ce0a23dSJerome Glisse }
36803ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD);
3681e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2);
36823ce0a23dSJerome Glisse if (r) {
36833ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
36843ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch);
36853ce0a23dSJerome Glisse return r;
36863ce0a23dSJerome Glisse }
3687e32eb50dSChristian König radeon_ring_write(ring, PACKET0(scratch, 0));
3688e32eb50dSChristian König radeon_ring_write(ring, 0xDEADBEEF);
36891538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false);
36903ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
36913ce0a23dSJerome Glisse tmp = RREG32(scratch);
36923ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) {
36933ce0a23dSJerome Glisse break;
36943ce0a23dSJerome Glisse }
36950e1a351dSSam Ravnborg udelay(1);
36963ce0a23dSJerome Glisse }
36973ce0a23dSJerome Glisse if (i < rdev->usec_timeout) {
36983ce0a23dSJerome Glisse DRM_INFO("ring test succeeded in %d usecs\n", i);
36993ce0a23dSJerome Glisse } else {
3700369d7ec1SAlex Deucher DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
37013ce0a23dSJerome Glisse scratch, tmp);
37023ce0a23dSJerome Glisse r = -EINVAL;
37033ce0a23dSJerome Glisse }
37043ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch);
37053ce0a23dSJerome Glisse return r;
37063ce0a23dSJerome Glisse }
37073ce0a23dSJerome Glisse
r100_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)37083ce0a23dSJerome Glisse void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
37093ce0a23dSJerome Glisse {
3710e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
37117b1f2485SChristian König
3712c7eff978SAlex Deucher if (ring->rptr_save_reg) {
3713c7eff978SAlex Deucher u32 next_rptr = ring->wptr + 2 + 3;
3714c7eff978SAlex Deucher radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3715c7eff978SAlex Deucher radeon_ring_write(ring, next_rptr);
3716c7eff978SAlex Deucher }
3717c7eff978SAlex Deucher
3718e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3719e32eb50dSChristian König radeon_ring_write(ring, ib->gpu_addr);
3720e32eb50dSChristian König radeon_ring_write(ring, ib->length_dw);
37213ce0a23dSJerome Glisse }
37223ce0a23dSJerome Glisse
r100_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)3723f712812eSAlex Deucher int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
37243ce0a23dSJerome Glisse {
3725f2e39221SJerome Glisse struct radeon_ib ib;
37263ce0a23dSJerome Glisse uint32_t scratch;
37273ce0a23dSJerome Glisse uint32_t tmp = 0;
37283ce0a23dSJerome Glisse unsigned i;
37293ce0a23dSJerome Glisse int r;
37303ce0a23dSJerome Glisse
37313ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch);
37323ce0a23dSJerome Glisse if (r) {
37333ce0a23dSJerome Glisse DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
37343ce0a23dSJerome Glisse return r;
37353ce0a23dSJerome Glisse }
37363ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD);
37374bf3dd92SChristian König r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
37383ce0a23dSJerome Glisse if (r) {
3739af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3740af026c5bSMichel Dänzer goto free_scratch;
37413ce0a23dSJerome Glisse }
3742f2e39221SJerome Glisse ib.ptr[0] = PACKET0(scratch, 0);
3743f2e39221SJerome Glisse ib.ptr[1] = 0xDEADBEEF;
3744f2e39221SJerome Glisse ib.ptr[2] = PACKET2(0);
3745f2e39221SJerome Glisse ib.ptr[3] = PACKET2(0);
3746f2e39221SJerome Glisse ib.ptr[4] = PACKET2(0);
3747f2e39221SJerome Glisse ib.ptr[5] = PACKET2(0);
3748f2e39221SJerome Glisse ib.ptr[6] = PACKET2(0);
3749f2e39221SJerome Glisse ib.ptr[7] = PACKET2(0);
3750f2e39221SJerome Glisse ib.length_dw = 8;
37511538a9e0SMichel Dänzer r = radeon_ib_schedule(rdev, &ib, NULL, false);
37523ce0a23dSJerome Glisse if (r) {
3753af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3754af026c5bSMichel Dänzer goto free_ib;
37553ce0a23dSJerome Glisse }
375604db4cafSMatthew Dawson r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
375704db4cafSMatthew Dawson RADEON_USEC_IB_TEST_TIMEOUT));
375804db4cafSMatthew Dawson if (r < 0) {
3759af026c5bSMichel Dänzer DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3760af026c5bSMichel Dänzer goto free_ib;
376104db4cafSMatthew Dawson } else if (r == 0) {
376204db4cafSMatthew Dawson DRM_ERROR("radeon: fence wait timed out.\n");
376304db4cafSMatthew Dawson r = -ETIMEDOUT;
376404db4cafSMatthew Dawson goto free_ib;
37653ce0a23dSJerome Glisse }
376604db4cafSMatthew Dawson r = 0;
37673ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) {
37683ce0a23dSJerome Glisse tmp = RREG32(scratch);
37693ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) {
37703ce0a23dSJerome Glisse break;
37713ce0a23dSJerome Glisse }
37720e1a351dSSam Ravnborg udelay(1);
37733ce0a23dSJerome Glisse }
37743ce0a23dSJerome Glisse if (i < rdev->usec_timeout) {
37753ce0a23dSJerome Glisse DRM_INFO("ib test succeeded in %u usecs\n", i);
37763ce0a23dSJerome Glisse } else {
377762f288cfSPaul Bolle DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
37783ce0a23dSJerome Glisse scratch, tmp);
37793ce0a23dSJerome Glisse r = -EINVAL;
37803ce0a23dSJerome Glisse }
3781af026c5bSMichel Dänzer free_ib:
37823ce0a23dSJerome Glisse radeon_ib_free(rdev, &ib);
3783af026c5bSMichel Dänzer free_scratch:
3784af026c5bSMichel Dänzer radeon_scratch_free(rdev, scratch);
37853ce0a23dSJerome Glisse return r;
37863ce0a23dSJerome Glisse }
37879f022ddfSJerome Glisse
r100_mc_stop(struct radeon_device * rdev,struct r100_mc_save * save)37889f022ddfSJerome Glisse void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
37899f022ddfSJerome Glisse {
37909f022ddfSJerome Glisse /* Shutdown CP we shouldn't need to do that but better be safe than
37919f022ddfSJerome Glisse * sorry
37929f022ddfSJerome Glisse */
3793e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
37949f022ddfSJerome Glisse WREG32(R_000740_CP_CSQ_CNTL, 0);
37959f022ddfSJerome Glisse
37969f022ddfSJerome Glisse /* Save few CRTC registers */
3797ca6ffc64SJerome Glisse save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
37989f022ddfSJerome Glisse save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
37999f022ddfSJerome Glisse save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
38009f022ddfSJerome Glisse save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
38019f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
38029f022ddfSJerome Glisse save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
38039f022ddfSJerome Glisse save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
38049f022ddfSJerome Glisse }
38059f022ddfSJerome Glisse
38069f022ddfSJerome Glisse /* Disable VGA aperture access */
3807ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
38089f022ddfSJerome Glisse /* Disable cursor, overlay, crtc */
38099f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
38109f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
38119f022ddfSJerome Glisse S_000054_CRTC_DISPLAY_DIS(1));
38129f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL,
38139f022ddfSJerome Glisse (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
38149f022ddfSJerome Glisse S_000050_CRTC_DISP_REQ_EN_B(1));
38159f022ddfSJerome Glisse WREG32(R_000420_OV0_SCALE_CNTL,
38169f022ddfSJerome Glisse C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
38179f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
38189f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
38199f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
38209f022ddfSJerome Glisse S_000360_CUR2_LOCK(1));
38219f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL,
38229f022ddfSJerome Glisse (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
38239f022ddfSJerome Glisse S_0003F8_CRTC2_DISPLAY_DIS(1) |
38249f022ddfSJerome Glisse S_0003F8_CRTC2_DISP_REQ_EN_B(1));
38259f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET,
38269f022ddfSJerome Glisse C_000360_CUR2_LOCK & save->CUR2_OFFSET);
38279f022ddfSJerome Glisse }
38289f022ddfSJerome Glisse }
38299f022ddfSJerome Glisse
r100_mc_resume(struct radeon_device * rdev,struct r100_mc_save * save)38309f022ddfSJerome Glisse void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
38319f022ddfSJerome Glisse {
38329f022ddfSJerome Glisse /* Update base address for crtc */
3833d594e46aSJerome Glisse WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
38349f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3835d594e46aSJerome Glisse WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
38369f022ddfSJerome Glisse }
38379f022ddfSJerome Glisse /* Restore CRTC registers */
3838ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
38399f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
38409f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
38419f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
38429f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
38439f022ddfSJerome Glisse }
38449f022ddfSJerome Glisse }
3845ca6ffc64SJerome Glisse
r100_vga_render_disable(struct radeon_device * rdev)3846ca6ffc64SJerome Glisse void r100_vga_render_disable(struct radeon_device *rdev)
3847ca6ffc64SJerome Glisse {
3848ca6ffc64SJerome Glisse u32 tmp;
3849ca6ffc64SJerome Glisse
3850ca6ffc64SJerome Glisse tmp = RREG8(R_0003C2_GENMO_WT);
3851ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3852ca6ffc64SJerome Glisse }
3853d4550907SJerome Glisse
r100_mc_program(struct radeon_device * rdev)3854d4550907SJerome Glisse static void r100_mc_program(struct radeon_device *rdev)
3855d4550907SJerome Glisse {
3856d4550907SJerome Glisse struct r100_mc_save save;
3857d4550907SJerome Glisse
3858d4550907SJerome Glisse /* Stops all mc clients */
3859d4550907SJerome Glisse r100_mc_stop(rdev, &save);
3860d4550907SJerome Glisse if (rdev->flags & RADEON_IS_AGP) {
3861d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION,
3862d4550907SJerome Glisse S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3863d4550907SJerome Glisse S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3864d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3865d4550907SJerome Glisse if (rdev->family > CHIP_RV200)
3866d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2,
3867d4550907SJerome Glisse upper_32_bits(rdev->mc.agp_base) & 0xff);
3868d4550907SJerome Glisse } else {
3869d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3870d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, 0);
3871d4550907SJerome Glisse if (rdev->family > CHIP_RV200)
3872d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 0);
3873d4550907SJerome Glisse }
3874d4550907SJerome Glisse /* Wait for mc idle */
3875d4550907SJerome Glisse if (r100_mc_wait_for_idle(rdev))
3876d4550907SJerome Glisse dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3877d4550907SJerome Glisse /* Program MC, should be a 32bits limited address space */
3878d4550907SJerome Glisse WREG32(R_000148_MC_FB_LOCATION,
3879d4550907SJerome Glisse S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3880d4550907SJerome Glisse S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3881d4550907SJerome Glisse r100_mc_resume(rdev, &save);
3882d4550907SJerome Glisse }
3883d4550907SJerome Glisse
r100_clock_startup(struct radeon_device * rdev)38841109ca09SLauri Kasanen static void r100_clock_startup(struct radeon_device *rdev)
3885d4550907SJerome Glisse {
3886d4550907SJerome Glisse u32 tmp;
3887d4550907SJerome Glisse
3888d4550907SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks)
3889d4550907SJerome Glisse radeon_legacy_set_clock_gating(rdev, 1);
3890d4550907SJerome Glisse /* We need to force on some of the block */
3891d4550907SJerome Glisse tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3892d4550907SJerome Glisse tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3893d4550907SJerome Glisse if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3894d4550907SJerome Glisse tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3895d4550907SJerome Glisse WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3896d4550907SJerome Glisse }
3897d4550907SJerome Glisse
r100_startup(struct radeon_device * rdev)3898d4550907SJerome Glisse static int r100_startup(struct radeon_device *rdev)
3899d4550907SJerome Glisse {
3900d4550907SJerome Glisse int r;
3901d4550907SJerome Glisse
390292cde00cSAlex Deucher /* set common regs */
390392cde00cSAlex Deucher r100_set_common_regs(rdev);
390492cde00cSAlex Deucher /* program mc */
3905d4550907SJerome Glisse r100_mc_program(rdev);
3906d4550907SJerome Glisse /* Resume clock */
3907d4550907SJerome Glisse r100_clock_startup(rdev);
3908d4550907SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate
3909d4550907SJerome Glisse * memory through TTM but finalize after TTM) */
391017e15b0cSDave Airlie r100_enable_bm(rdev);
3911d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) {
3912d4550907SJerome Glisse r = r100_pci_gart_enable(rdev);
3913d4550907SJerome Glisse if (r)
3914d4550907SJerome Glisse return r;
3915d4550907SJerome Glisse }
3916724c80e1SAlex Deucher
3917724c80e1SAlex Deucher /* allocate wb buffer */
3918724c80e1SAlex Deucher r = radeon_wb_init(rdev);
3919724c80e1SAlex Deucher if (r)
3920724c80e1SAlex Deucher return r;
3921724c80e1SAlex Deucher
392230eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
392330eb77f4SJerome Glisse if (r) {
392430eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
392530eb77f4SJerome Glisse return r;
392630eb77f4SJerome Glisse }
392730eb77f4SJerome Glisse
3928d4550907SJerome Glisse /* Enable IRQ */
3929e49f3959SAdis Hamzić if (!rdev->irq.installed) {
3930e49f3959SAdis Hamzić r = radeon_irq_kms_init(rdev);
3931e49f3959SAdis Hamzić if (r)
3932e49f3959SAdis Hamzić return r;
3933e49f3959SAdis Hamzić }
3934e49f3959SAdis Hamzić
3935d4550907SJerome Glisse r100_irq_set(rdev);
3936cafe6609SJerome Glisse rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3937d4550907SJerome Glisse /* 1M ring buffer */
3938d4550907SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024);
3939d4550907SJerome Glisse if (r) {
3940ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3941d4550907SJerome Glisse return r;
3942d4550907SJerome Glisse }
3943b15ba512SJerome Glisse
39442898c348SChristian König r = radeon_ib_pool_init(rdev);
39452898c348SChristian König if (r) {
39462898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3947b15ba512SJerome Glisse return r;
39482898c348SChristian König }
3949b15ba512SJerome Glisse
3950d4550907SJerome Glisse return 0;
3951d4550907SJerome Glisse }
3952d4550907SJerome Glisse
r100_resume(struct radeon_device * rdev)3953d4550907SJerome Glisse int r100_resume(struct radeon_device *rdev)
3954d4550907SJerome Glisse {
39556b7746e8SJerome Glisse int r;
39566b7746e8SJerome Glisse
3957d4550907SJerome Glisse /* Make sur GART are not working */
3958d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI)
3959d4550907SJerome Glisse r100_pci_gart_disable(rdev);
3960d4550907SJerome Glisse /* Resume clock before doing reset */
3961d4550907SJerome Glisse r100_clock_startup(rdev);
3962d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3963a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) {
3964d4550907SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3965d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS),
3966d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT));
3967d4550907SJerome Glisse }
3968d4550907SJerome Glisse /* post */
3969*5e3a0f77SWu Hoi Pok radeon_combios_asic_init(rdev_to_drm(rdev));
3970d4550907SJerome Glisse /* Resume clock after posting */
3971d4550907SJerome Glisse r100_clock_startup(rdev);
3972550e2d92SDave Airlie /* Initialize surface registers */
3973550e2d92SDave Airlie radeon_surface_init(rdev);
3974b15ba512SJerome Glisse
3975b15ba512SJerome Glisse rdev->accel_working = true;
39766b7746e8SJerome Glisse r = r100_startup(rdev);
39776b7746e8SJerome Glisse if (r) {
39786b7746e8SJerome Glisse rdev->accel_working = false;
39796b7746e8SJerome Glisse }
39806b7746e8SJerome Glisse return r;
3981d4550907SJerome Glisse }
3982d4550907SJerome Glisse
r100_suspend(struct radeon_device * rdev)3983d4550907SJerome Glisse int r100_suspend(struct radeon_device *rdev)
3984d4550907SJerome Glisse {
39856c7bcceaSAlex Deucher radeon_pm_suspend(rdev);
3986d4550907SJerome Glisse r100_cp_disable(rdev);
3987724c80e1SAlex Deucher radeon_wb_disable(rdev);
3988d4550907SJerome Glisse r100_irq_disable(rdev);
3989d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI)
3990d4550907SJerome Glisse r100_pci_gart_disable(rdev);
3991d4550907SJerome Glisse return 0;
3992d4550907SJerome Glisse }
3993d4550907SJerome Glisse
r100_fini(struct radeon_device * rdev)3994d4550907SJerome Glisse void r100_fini(struct radeon_device *rdev)
3995d4550907SJerome Glisse {
39966c7bcceaSAlex Deucher radeon_pm_fini(rdev);
3997d4550907SJerome Glisse r100_cp_fini(rdev);
3998724c80e1SAlex Deucher radeon_wb_fini(rdev);
39992898c348SChristian König radeon_ib_pool_fini(rdev);
4000d4550907SJerome Glisse radeon_gem_fini(rdev);
4001d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI)
4002d4550907SJerome Glisse r100_pci_gart_fini(rdev);
4003d0269ed8SJerome Glisse radeon_agp_fini(rdev);
4004d4550907SJerome Glisse radeon_irq_kms_fini(rdev);
4005d4550907SJerome Glisse radeon_fence_driver_fini(rdev);
40064c788679SJerome Glisse radeon_bo_fini(rdev);
4007d4550907SJerome Glisse radeon_atombios_fini(rdev);
4008d4550907SJerome Glisse kfree(rdev->bios);
4009d4550907SJerome Glisse rdev->bios = NULL;
4010d4550907SJerome Glisse }
4011d4550907SJerome Glisse
40124c712e6cSDave Airlie /*
40134c712e6cSDave Airlie * Due to how kexec works, it can leave the hw fully initialised when it
40144c712e6cSDave Airlie * boots the new kernel. However doing our init sequence with the CP and
40154c712e6cSDave Airlie * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
40164c712e6cSDave Airlie * do some quick sanity checks and restore sane values to avoid this
40174c712e6cSDave Airlie * problem.
40184c712e6cSDave Airlie */
r100_restore_sanity(struct radeon_device * rdev)40194c712e6cSDave Airlie void r100_restore_sanity(struct radeon_device *rdev)
40204c712e6cSDave Airlie {
40214c712e6cSDave Airlie u32 tmp;
40224c712e6cSDave Airlie
40234c712e6cSDave Airlie tmp = RREG32(RADEON_CP_CSQ_CNTL);
40244c712e6cSDave Airlie if (tmp) {
40254c712e6cSDave Airlie WREG32(RADEON_CP_CSQ_CNTL, 0);
40264c712e6cSDave Airlie }
40274c712e6cSDave Airlie tmp = RREG32(RADEON_CP_RB_CNTL);
40284c712e6cSDave Airlie if (tmp) {
40294c712e6cSDave Airlie WREG32(RADEON_CP_RB_CNTL, 0);
40304c712e6cSDave Airlie }
40314c712e6cSDave Airlie tmp = RREG32(RADEON_SCRATCH_UMSK);
40324c712e6cSDave Airlie if (tmp) {
40334c712e6cSDave Airlie WREG32(RADEON_SCRATCH_UMSK, 0);
40344c712e6cSDave Airlie }
40354c712e6cSDave Airlie }
40364c712e6cSDave Airlie
r100_init(struct radeon_device * rdev)4037d4550907SJerome Glisse int r100_init(struct radeon_device *rdev)
4038d4550907SJerome Glisse {
4039d4550907SJerome Glisse int r;
4040d4550907SJerome Glisse
4041d4550907SJerome Glisse /* Register debugfs file specific to this group of asics */
40425b54d679SNirmoy Das r100_debugfs_mc_info_init(rdev);
4043d4550907SJerome Glisse /* Disable VGA */
4044d4550907SJerome Glisse r100_vga_render_disable(rdev);
4045d4550907SJerome Glisse /* Initialize scratch registers */
4046d4550907SJerome Glisse radeon_scratch_init(rdev);
4047d4550907SJerome Glisse /* Initialize surface registers */
4048d4550907SJerome Glisse radeon_surface_init(rdev);
40494c712e6cSDave Airlie /* sanity check some register to avoid hangs like after kexec */
40504c712e6cSDave Airlie r100_restore_sanity(rdev);
4051d4550907SJerome Glisse /* TODO: disable VGA need to use VGA request */
4052d4550907SJerome Glisse /* BIOS*/
4053d4550907SJerome Glisse if (!radeon_get_bios(rdev)) {
4054d4550907SJerome Glisse if (ASIC_IS_AVIVO(rdev))
4055d4550907SJerome Glisse return -EINVAL;
4056d4550907SJerome Glisse }
4057d4550907SJerome Glisse if (rdev->is_atom_bios) {
4058d4550907SJerome Glisse dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4059d4550907SJerome Glisse return -EINVAL;
4060d4550907SJerome Glisse } else {
4061d4550907SJerome Glisse r = radeon_combios_init(rdev);
4062d4550907SJerome Glisse if (r)
4063d4550907SJerome Glisse return r;
4064d4550907SJerome Glisse }
4065d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4066a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) {
4067d4550907SJerome Glisse dev_warn(rdev->dev,
4068d4550907SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4069d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS),
4070d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT));
4071d4550907SJerome Glisse }
4072d4550907SJerome Glisse /* check if cards are posted or not */
407372542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false)
407472542d77SDave Airlie return -EINVAL;
4075d4550907SJerome Glisse /* Set asic errata */
4076d4550907SJerome Glisse r100_errata(rdev);
4077d4550907SJerome Glisse /* Initialize clocks */
4078*5e3a0f77SWu Hoi Pok radeon_get_clock_info(rdev_to_drm(rdev));
4079d594e46aSJerome Glisse /* initialize AGP */
4080d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) {
4081d594e46aSJerome Glisse r = radeon_agp_init(rdev);
4082d594e46aSJerome Glisse if (r) {
4083d594e46aSJerome Glisse radeon_agp_disable(rdev);
4084d594e46aSJerome Glisse }
4085d594e46aSJerome Glisse }
4086d594e46aSJerome Glisse /* initialize VRAM */
4087d594e46aSJerome Glisse r100_mc_init(rdev);
4088d4550907SJerome Glisse /* Fence driver */
4089519424d7SBernard Zhao radeon_fence_driver_init(rdev);
4090d4550907SJerome Glisse /* Memory manager */
40914c788679SJerome Glisse r = radeon_bo_init(rdev);
4092d4550907SJerome Glisse if (r)
4093d4550907SJerome Glisse return r;
4094d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) {
4095d4550907SJerome Glisse r = r100_pci_gart_init(rdev);
4096d4550907SJerome Glisse if (r)
4097d4550907SJerome Glisse return r;
4098d4550907SJerome Glisse }
4099d4550907SJerome Glisse r100_set_safe_registers(rdev);
4100b15ba512SJerome Glisse
41016c7bcceaSAlex Deucher /* Initialize power management */
41026c7bcceaSAlex Deucher radeon_pm_init(rdev);
41036c7bcceaSAlex Deucher
4104d4550907SJerome Glisse rdev->accel_working = true;
4105d4550907SJerome Glisse r = r100_startup(rdev);
4106d4550907SJerome Glisse if (r) {
4107d4550907SJerome Glisse /* Somethings want wront with the accel init stop accel */
4108d4550907SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n");
4109d4550907SJerome Glisse r100_cp_fini(rdev);
4110724c80e1SAlex Deucher radeon_wb_fini(rdev);
41112898c348SChristian König radeon_ib_pool_fini(rdev);
4112655efd3dSJerome Glisse radeon_irq_kms_fini(rdev);
4113d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI)
4114d4550907SJerome Glisse r100_pci_gart_fini(rdev);
4115d4550907SJerome Glisse rdev->accel_working = false;
4116d4550907SJerome Glisse }
4117d4550907SJerome Glisse return 0;
4118d4550907SJerome Glisse }
41196fcbef7aSAndi Kleen
r100_mm_rreg_slow(struct radeon_device * rdev,uint32_t reg)41209e5acbc2SDenys Vlasenko uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
41219e5acbc2SDenys Vlasenko {
41229e5acbc2SDenys Vlasenko unsigned long flags;
41239e5acbc2SDenys Vlasenko uint32_t ret;
41249e5acbc2SDenys Vlasenko
41259e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
41269e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
41279e5acbc2SDenys Vlasenko ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
41289e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
41299e5acbc2SDenys Vlasenko return ret;
41309e5acbc2SDenys Vlasenko }
41319e5acbc2SDenys Vlasenko
r100_mm_wreg_slow(struct radeon_device * rdev,uint32_t reg,uint32_t v)41329e5acbc2SDenys Vlasenko void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
41339e5acbc2SDenys Vlasenko {
41349e5acbc2SDenys Vlasenko unsigned long flags;
41359e5acbc2SDenys Vlasenko
41369e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
41379e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
41389e5acbc2SDenys Vlasenko writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
41399e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
41409e5acbc2SDenys Vlasenko }
41419e5acbc2SDenys Vlasenko
r100_io_rreg(struct radeon_device * rdev,u32 reg)41426fcbef7aSAndi Kleen u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
41436fcbef7aSAndi Kleen {
41446fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size)
41456fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + reg);
41466fcbef7aSAndi Kleen else {
41476fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
41486fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + RADEON_MM_DATA);
41496fcbef7aSAndi Kleen }
41506fcbef7aSAndi Kleen }
41516fcbef7aSAndi Kleen
r100_io_wreg(struct radeon_device * rdev,u32 reg,u32 v)41526fcbef7aSAndi Kleen void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
41536fcbef7aSAndi Kleen {
41546fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size)
41556fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + reg);
41566fcbef7aSAndi Kleen else {
41576fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
41586fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
41596fcbef7aSAndi Kleen }
41606fcbef7aSAndi Kleen }
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