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Searched refs:RISCV_EXCP_LOAD_ADDR_MIS (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h678 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, enumerator
H A Dcpu_helper.c1388 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; in riscv_cpu_do_unaligned_access()
1827 case RISCV_EXCP_LOAD_ADDR_MIS: in riscv_cpu_do_interrupt()
H A Dcsr.c1401 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \