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Searched refs:RISCV_EXCP_INT_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h704 #define RISCV_EXCP_INT_MASK 0x7fffffff macro
H A Dcpu_helper.c1803 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; in riscv_cpu_do_interrupt()