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Searched refs:REG_PAD_CTRL1 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8723b.c557 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
559 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
1450 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); in rtl8723bu_power_on()
1470 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723bu_power_on()
1472 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723bu_power_on()
1592 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723b_enable_rf()
1594 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723b_enable_rf()
H A Drtl8xxxu_8192e.c1681 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8192e_enable_rf()
1683 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8192e_enable_rf()
H A Drtl8xxxu_8192f.c1561 rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); in rtl8192fu_phy_iq_calibrate()
1628 rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); in rtl8192fu_emu_to_active()
H A Drtl8xxxu_regs.h173 #define REG_PAD_CTRL1 0x0064 macro
H A Drtl8xxxu_8188e.c1271 rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808); in rtl8188eu_power_off()
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d.c795 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723d_iqk_config_path_ctrl()
797 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_config_path_ctrl()
805 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_restore_path_ctrl()
984 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_tx_path()
1045 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_rx_path()
1104 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_rx_path()
1576 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); in rtw8723d_coex_cfg_gnt_debug()
1579 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1580 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); in rtw8723d_coex_cfg_gnt_debug()
H A Drtw8821c.c882 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, in rtw8821c_coex_cfg_ant_switch()
909 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN); in rtw8821c_coex_cfg_gnt_debug()
910 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN); in rtw8821c_coex_cfg_gnt_debug()
912 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS); in rtw8821c_coex_cfg_gnt_debug()
H A Drtw8822b.c1228 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); in rtw8822b_coex_cfg_ant_switch()
1251 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1252 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1254 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822b_coex_cfg_gnt_debug()
H A Dreg.h74 #define REG_PAD_CTRL1 0x0064 macro
H A Dmac.c111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); in rtw_mac_pre_system_cfg()
113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); in rtw_mac_pre_system_cfg()
H A Drtw8822c.c3070 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822c_coex_cfg_gnt_debug()
3071 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822c_coex_cfg_gnt_debug()
3073 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822c_coex_cfg_gnt_debug()