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Searched refs:REG_OFDM0_XA_AGC_CORE1 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8188f.c471 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188f_spur_calibration()
480 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188f_spur_calibration()
506 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); in rtl8188f_spur_calibration()
1111 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1220 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1223 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1224 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1227 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
H A Drtl8xxxu_8710b.c1304 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8710bu_phy_iqcalibrate()
1410 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8710bu_phy_iqcalibrate()
1412 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8710bu_phy_iqcalibrate()
1413 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8710bu_phy_iqcalibrate()
1415 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8710bu_phy_iqcalibrate()
H A Drtl8xxxu_8192e.c1093 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1232 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1234 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1235 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
H A Drtl8xxxu_8723b.c937 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
1098 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1100 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1101 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
H A Drtl8xxxu_8192f.c1301 rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192fu_phy_iqcalibrate()
1447 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50); in rtl8192fu_phy_iqcalibrate()
1448 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, in rtl8192fu_phy_iqcalibrate()
H A Drtl8xxxu_regs.h1068 #define REG_OFDM0_XA_AGC_CORE1 0x0c50 macro
H A Drtl8xxxu_core.c7259 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, in rtl8xxxu_start()